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HFGITR_EL2

Hypervisor Fine-Grained Instruction Trap Register

Provides instruction trap controls.

Configuration

This register is present only when FEAT_FGT is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to HFGITR_EL2 are UNDEFINED.

If EL2 is not implemented, this register is RES0 from EL3.

Attributes

HFGITR_EL2 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
PSBCSYNCATS1E1ARES0COSPRCTXnGCSEPPnGCSSTR_EL1nGCSPUSHM_EL1nBRBIALLnBRBINJDCCVACSVC_EL1SVC_EL0ERETCPPRCTXDVPRCTXCFPRCTXTLBIVAALE1TLBIVALE1TLBIVAAE1TLBIASIDE1TLBIVAE1TLBIVMALLE1TLBIRVAALE1TLBIRVALE1TLBIRVAAE1TLBIRVAE1TLBIRVAALE1ISTLBIRVALE1ISTLBIRVAAE1ISTLBIRVAE1ISTLBIVAALE1ISTLBIVALE1IS
TLBIVAAE1ISTLBIASIDE1ISTLBIVAE1ISTLBIVMALLE1ISTLBIRVAALE1OSTLBIRVALE1OSTLBIRVAAE1OSTLBIRVAE1OSTLBIVAALE1OSTLBIVALE1OSTLBIVAAE1OSTLBIASIDE1OSTLBIVAE1OSTLBIVMALLE1OSATS1E1WPATS1E1RPATS1E0WATS1E0RATS1E1WATS1E1RDCZVADCCIVACDCCVADPDCCVAPDCCVAUDCCISWDCCSWDCISWDCIVACICIVAUICIALLUICIALLUIS

PSBCSYNC, bit [63] when FEAT_SPEv1p5 is implemented:

Trap execution of PSB CSYNC at EL1 and EL0 using AArch64 to EL2.

PSBCSYNCMeaning
0b0

Execution of PSB CSYNC is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of PSB CSYNC at EL1 and EL0 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x0A, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

ATS1E1A, bit [62] when FEAT_ATS1A is implemented:

Trap execution of AT S1E1A at EL1 using AArch64 to EL2.

ATS1E1AMeaning
0b0

Execution of AT S1E1A is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of AT S1E1A at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Bit [61]:

Reserved, RES0.

COSPRCTX, bit [60] when FEAT_SPECRES2 is implemented:

Trap execution of COSP RCTX at EL1 and EL0 using AArch64 and execution of COSPRCTX at EL0 using AArch32 when EL1 is using AArch64 to EL2.

COSPRCTXMeaning
0b0

Execution of COSP RCTX at EL1 and EL0 using AArch64 and execution of COSPRCTX at EL0 using AArch32 are not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then unless the instruction generates a higher priority exception:

  • Execution of COSP RCTX at EL1 and EL0 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18.
  • Execution of COSPRCTX at EL0 using AArch32 when EL1 is using AArch64 is trapped to EL2 and reported with EC syndrome value 0x03.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

nGCSEPP, bit [59] when FEAT_GCS is implemented:

Trap execution of any of the following AArch64 instructions at EL1 to EL2:

nGCSEPPMeaning
0b0

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution at EL1 using AArch64 of any of the specified instructions is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

0b1

Execution of the specified instructions is not trapped by this mechanism.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

nGCSSTR_EL1, bit [58] when FEAT_GCS is implemented:

Trap execution of any of the following AArch64 instructions at EL1 to EL2:

nGCSSTR_EL1Meaning
0b0

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution at EL1 using AArch64 of any of the specified instructions generates a GCS exception with EC syndrome value 0x2D, unless the instruction generates a higher priority exception.

0b1

Execution of the specified instructions is not trapped by this mechanism.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

nGCSPUSHM_EL1, bit [57] when FEAT_GCS is implemented:

Trap execution of GCSPUSHM at EL1 using AArch64 to EL2.

nGCSPUSHM_EL1Meaning
0b0

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of GCSPUSHM at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

0b1

Execution of GCSPUSHM is not trapped by this mechanism.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

nBRBIALL, bit [56] when FEAT_BRBE is implemented:

Trap execution of BRB IALL at EL1 using AArch64 to EL2.

nBRBIALLMeaning
0b0

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of BRB IALL at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

0b1

Execution of BRB IALL is not trapped by this mechanism.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

nBRBINJ, bit [55] when FEAT_BRBE is implemented:

Trap execution of BRB INJ at EL1 using AArch64 to EL2.

nBRBINJMeaning
0b0

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of BRB INJ at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

0b1

Execution of BRB INJ is not trapped by this mechanism.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

DCCVAC, bit [54]:

Trap execution of any of the following AArch64 instructions at EL1 and EL0 to EL2:

DCCVACMeaning
0b0

Execution of the specified instructions is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then if the execution can be trapped, execution at EL1 and EL0 using AArch64 of any of the specified instructions is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

SVC_EL1, bit [53]:

Trap execution of SVC at EL1 using AArch64 to EL2.

SVC_EL1Meaning
0b0

Execution of SVC is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of SVC at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x15, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

SVC_EL0, bit [52]:

Trap execution of SVC at EL0 using AArch64 and execution of SVC at EL0 using AArch32 when EL1 is using AArch64 to EL2.

SVC_EL0Meaning
0b0

Execution of SVC at EL0 using AArch64 and execution of SVC at EL0 using AArch32 are not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then unless the instruction generates a higher priority exception:

  • Execution of SVC at EL0 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x15.
  • Execution of SVC at EL0 using AArch32 when EL1 is using AArch64 is trapped to EL2 and reported with EC syndrome value 0x11.

The reset behavior of this field is:

ERET, bit [51]:

Trap execution of any of the following AArch64 instructions at EL1 to EL2:

ERETMeaning
0b0

Execution of the specified instructions is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution at EL1 using AArch64 of any of the specified instructions is trapped to EL2 and reported with EC syndrome value 0x1A, unless the instruction generates a higher priority exception.

If EL2 is implemented and enabled in the current Security state, HCR_EL2.API == 0, and this field enables a fine-grained trap on the instruction, then execution at EL1 using AArch64 of ERETAA or ERETAB instructions is trapped to EL2 and reported with EC syndrome value 0x1A with its associated ISS field, as the fine-grained trap has higher priority than the trap enabled by HCR_EL2.API == 0.

The reset behavior of this field is:

CPPRCTX, bit [50] when FEAT_SPECRES is implemented:

Trap execution of CPP RCTX at EL1 and EL0 using AArch64 and execution of CPPRCTX at EL0 using AArch32 when EL1 is using AArch64 to EL2.

CPPRCTXMeaning
0b0

Execution of CPP RCTX at EL1 and EL0 using AArch64 and execution of CPPRCTX at EL0 using AArch32 are not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then unless the instruction generates a higher priority exception:

  • Execution of CPP RCTX at EL1 and EL0 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18.
  • Execution of CPPRCTX at EL0 using AArch32 when EL1 is using AArch64 is trapped to EL2 and reported with EC syndrome value 0x03.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

DVPRCTX, bit [49] when FEAT_SPECRES is implemented:

Trap execution of DVP RCTX at EL1 and EL0 using AArch64 and execution of DVPRCTX at EL0 using AArch32 when EL1 is using AArch64 to EL2.

DVPRCTXMeaning
0b0

Execution of DVP RCTX at EL1 and EL0 using AArch64 and execution of DVPRCTX at EL0 using AArch32 are not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then unless the instruction generates a higher priority exception:

  • Execution of DVP RCTX at EL1 and EL0 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18.
  • Execution of DVPRCTX at EL0 using AArch32 when EL1 is using AArch64 is trapped to EL2 and reported with EC syndrome value 0x03.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

CFPRCTX, bit [48] when FEAT_SPECRES is implemented:

Trap execution of CFP RCTX at EL1 and EL0 using AArch64 and execution of CFPRCTX at EL0 using AArch32 when EL1 is using AArch64 to EL2.

CFPRCTXMeaning
0b0

Execution of CFP RCTX at EL1 and EL0 using AArch64 and execution of CFPRCTX at EL0 using AArch32 are not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then unless the instruction generates a higher priority exception:

  • Execution of CFP RCTX at EL1 and EL0 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18.
  • Execution of CFPRCTX at EL0 using AArch32 when EL1 is using AArch64 is trapped to EL2 and reported with EC syndrome value 0x03.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TLBIVAALE1, bit [47]:

Trap execution of TLBI VAALE1 at EL1 using AArch64 to EL2.

If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI VAALE1NXS.

If FEAT_D128 is implemented, then this field also traps execution of TLBIP VAALE1.

If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP VAALE1NXS.

TLBIVAALE1Meaning
0b0

Execution of TLBI VAALE1 is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI VAALE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

TLBIVALE1, bit [46]:

Trap execution of TLBI VALE1 at EL1 using AArch64 to EL2.

If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI VALE1NXS.

If FEAT_D128 is implemented, then this field also traps execution of TLBIP VALE1.

If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP VALE1NXS.

TLBIVALE1Meaning
0b0

Execution of TLBI VALE1 is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI VALE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

TLBIVAAE1, bit [45]:

Trap execution of TLBI VAAE1 at EL1 using AArch64 to EL2.

If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI VAAE1NXS.

If FEAT_D128 is implemented, then this field also traps execution of TLBIP VAAE1.

If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP VAAE1NXS.

TLBIVAAE1Meaning
0b0

Execution of TLBI VAAE1 is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI VAAE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

TLBIASIDE1, bit [44]:

Trap execution of TLBI ASIDE1 at EL1 using AArch64 to EL2.

If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI ASIDE1NXS.

TLBIASIDE1Meaning
0b0

Execution of TLBI ASIDE1 is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI ASIDE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

TLBIVAE1, bit [43]:

Trap execution of TLBI VAE1 at EL1 using AArch64 to EL2.

If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI VAE1NXS.

If FEAT_D128 is implemented, then this field also traps execution of TLBIP VAE1.

If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP VAE1NXS.

TLBIVAE1Meaning
0b0

Execution of TLBI VAE1 is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI VAE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

TLBIVMALLE1, bit [42]:

Trap execution of TLBI VMALLE1 at EL1 using AArch64 to EL2.

If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI VMALLE1NXS.

TLBIVMALLE1Meaning
0b0

Execution of TLBI VMALLE1 is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI VMALLE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

TLBIRVAALE1, bit [41] when FEAT_TLBIRANGE is implemented:

Trap execution of TLBI RVAALE1 at EL1 using AArch64 to EL2.

If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI RVAALE1NXS.

If FEAT_D128 is implemented, then this field also traps execution of TLBIP RVAALE1.

If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP RVAALE1NXS.

TLBIRVAALE1Meaning
0b0

Execution of TLBI RVAALE1 is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI RVAALE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TLBIRVALE1, bit [40] when FEAT_TLBIRANGE is implemented:

Trap execution of TLBI RVALE1 at EL1 using AArch64 to EL2.

If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI RVALE1NXS.

If FEAT_D128 is implemented, then this field also traps execution of TLBIP RVALE1.

If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP RVALE1NXS.

TLBIRVALE1Meaning
0b0

Execution of TLBI RVALE1 is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI RVALE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TLBIRVAAE1, bit [39] when FEAT_TLBIRANGE is implemented:

Trap execution of TLBI RVAAE1 at EL1 using AArch64 to EL2.

If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI RVAAE1NXS.

If FEAT_D128 is implemented, then this field also traps execution of TLBIP RVAAE1.

If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP RVAAE1NXS.

TLBIRVAAE1Meaning
0b0

Execution of TLBI RVAAE1 is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI RVAAE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TLBIRVAE1, bit [38] when FEAT_TLBIRANGE is implemented:

Trap execution of TLBI RVAE1 at EL1 using AArch64 to EL2.

If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI RVAE1NXS.

If FEAT_D128 is implemented, then this field also traps execution of TLBIP RVAE1.

If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP RVAE1NXS.

TLBIRVAE1Meaning
0b0

Execution of TLBI RVAE1 is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI RVAE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TLBIRVAALE1IS, bit [37] when FEAT_TLBIRANGE is implemented:

Trap execution of TLBI RVAALE1IS at EL1 using AArch64 to EL2.

If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI RVAALE1ISNXS.

If FEAT_D128 is implemented, then this field also traps execution of TLBIP RVAALE1IS.

If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP RVAALE1ISNXS.

TLBIRVAALE1ISMeaning
0b0

Execution of TLBI RVAALE1IS is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI RVAALE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TLBIRVALE1IS, bit [36] when FEAT_TLBIRANGE is implemented:

Trap execution of TLBI RVALE1IS at EL1 using AArch64 to EL2.

If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI RVALE1ISNXS.

If FEAT_D128 is implemented, then this field also traps execution of TLBIP RVALE1IS.

If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP RVALE1ISNXS.

TLBIRVALE1ISMeaning
0b0

Execution of TLBI RVALE1IS is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI RVALE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TLBIRVAAE1IS, bit [35] when FEAT_TLBIRANGE is implemented:

Trap execution of TLBI RVAAE1IS at EL1 using AArch64 to EL2.

If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI RVAAE1ISNXS.

If FEAT_D128 is implemented, then this field also traps execution of TLBIP RVAAE1IS.

If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP RVAAE1ISNXS.

TLBIRVAAE1ISMeaning
0b0

Execution of TLBI RVAAE1IS is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI RVAAE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TLBIRVAE1IS, bit [34] when FEAT_TLBIRANGE is implemented:

Trap execution of TLBI RVAE1IS at EL1 using AArch64 to EL2.

If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI RVAE1ISNXS.

If FEAT_D128 is implemented, then this field also traps execution of TLBIP RVAE1IS.

If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP RVAE1ISNXS.

TLBIRVAE1ISMeaning
0b0

Execution of TLBI RVAE1IS is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI RVAE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TLBIVAALE1IS, bit [33]:

Trap execution of TLBI VAALE1IS at EL1 using AArch64 to EL2.

If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI VAALE1ISNXS.

If FEAT_D128 is implemented, then this field also traps execution of TLBIP VAALE1IS.

If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP VAALE1ISNXS.

TLBIVAALE1ISMeaning
0b0

Execution of TLBI VAALE1IS is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI VAALE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

TLBIVALE1IS, bit [32]:

Trap execution of TLBI VALE1IS at EL1 using AArch64 to EL2.

If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI VALE1ISNXS.

If FEAT_D128 is implemented, then this field also traps execution of TLBIP VALE1IS.

If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP VALE1ISNXS.

TLBIVALE1ISMeaning
0b0

Execution of TLBI VALE1IS is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI VALE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

TLBIVAAE1IS, bit [31]:

Trap execution of TLBI VAAE1IS at EL1 using AArch64 to EL2.

If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI VAAE1ISNXS.

If FEAT_D128 is implemented, then this field also traps execution of TLBIP VAAE1IS.

If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP VAAE1ISNXS.

TLBIVAAE1ISMeaning
0b0

Execution of TLBI VAAE1IS is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI VAAE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

TLBIASIDE1IS, bit [30]:

Trap execution of TLBI ASIDE1IS at EL1 using AArch64 to EL2.

If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI ASIDE1ISNXS.

TLBIASIDE1ISMeaning
0b0

Execution of TLBI ASIDE1IS is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI ASIDE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

TLBIVAE1IS, bit [29]:

Trap execution of TLBI VAE1IS at EL1 using AArch64 to EL2.

If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI VAE1ISNXS.

If FEAT_D128 is implemented, then this field also traps execution of TLBIP VAE1IS.

If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP VAE1ISNXS.

TLBIVAE1ISMeaning
0b0

Execution of TLBI VAE1IS is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI VAE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

TLBIVMALLE1IS, bit [28]:

Trap execution of TLBI VMALLE1IS at EL1 using AArch64 to EL2.

If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI VMALLE1ISNXS.

TLBIVMALLE1ISMeaning
0b0

Execution of TLBI VMALLE1IS is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI VMALLE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

TLBIRVAALE1OS, bit [27] when FEAT_TLBIRANGE is implemented and FEAT_TLBIOS is implemented:

Trap execution of TLBI RVAALE1OS at EL1 using AArch64 to EL2.

If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI RVAALE1OSNXS.

If FEAT_D128 is implemented, then this field also traps execution of TLBIP RVAALE1OS.

If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP RVAALE1OSNXS.

TLBIRVAALE1OSMeaning
0b0

Execution of TLBI RVAALE1OS is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI RVAALE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TLBIRVALE1OS, bit [26] when FEAT_TLBIRANGE is implemented and FEAT_TLBIOS is implemented:

Trap execution of TLBI RVALE1OS at EL1 using AArch64 to EL2.

If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI RVALE1OSNXS.

If FEAT_D128 is implemented, then this field also traps execution of TLBIP RVALE1OS.

If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP RVALE1OSNXS.

TLBIRVALE1OSMeaning
0b0

Execution of TLBI RVALE1OS is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI RVALE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TLBIRVAAE1OS, bit [25] when FEAT_TLBIRANGE is implemented and FEAT_TLBIOS is implemented:

Trap execution of TLBI RVAAE1OS at EL1 using AArch64 to EL2.

If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI RVAAE1OSNXS.

If FEAT_D128 is implemented, then this field also traps execution of TLBIP RVAAE1OS.

If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP RVAAE1OSNXS.

TLBIRVAAE1OSMeaning
0b0

Execution of TLBI RVAAE1OS is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI RVAAE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TLBIRVAE1OS, bit [24] when FEAT_TLBIRANGE is implemented and FEAT_TLBIOS is implemented:

Trap execution of TLBI RVAE1OS at EL1 using AArch64 to EL2.

If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI RVAE1OSNXS.

If FEAT_D128 is implemented, then this field also traps execution of TLBIP RVAE1OS.

If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP RVAE1OSNXS.

TLBIRVAE1OSMeaning
0b0

Execution of TLBI RVAE1OS is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI RVAE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TLBIVAALE1OS, bit [23] when FEAT_TLBIOS is implemented:

Trap execution of TLBI VAALE1OS at EL1 using AArch64 to EL2.

If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI VAALE1OSNXS.

If FEAT_D128 is implemented, then this field also traps execution of TLBIP VAALE1OS.

If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP VAALE1OSNXS.

TLBIVAALE1OSMeaning
0b0

Execution of TLBI VAALE1OS is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI VAALE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TLBIVALE1OS, bit [22] when FEAT_TLBIOS is implemented:

Trap execution of TLBI VALE1OS at EL1 using AArch64 to EL2.

If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI VALE1OSNXS.

If FEAT_D128 is implemented, then this field also traps execution of TLBIP VALE1OS.

If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP VALE1OSNXS.

TLBIVALE1OSMeaning
0b0

Execution of TLBI VALE1OS is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI VALE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TLBIVAAE1OS, bit [21] when FEAT_TLBIOS is implemented:

Trap execution of TLBI VAAE1OS at EL1 using AArch64 to EL2.

If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI VAAE1OSNXS.

If FEAT_D128 is implemented, then this field also traps execution of TLBIP VAAE1OS.

If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP VAAE1OSNXS.

TLBIVAAE1OSMeaning
0b0

Execution of TLBI VAAE1OS is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI VAAE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TLBIASIDE1OS, bit [20] when FEAT_TLBIOS is implemented:

Trap execution of TLBI ASIDE1OS at EL1 using AArch64 to EL2.

If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI ASIDE1OSNXS.

TLBIASIDE1OSMeaning
0b0

Execution of TLBI ASIDE1OS is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI ASIDE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TLBIVAE1OS, bit [19] when FEAT_TLBIOS is implemented:

Trap execution of TLBI VAE1OS at EL1 using AArch64 to EL2.

If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI VAE1OSNXS.

If FEAT_D128 is implemented, then this field also traps execution of TLBIP VAE1OS.

If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP VAE1OSNXS.

TLBIVAE1OSMeaning
0b0

Execution of TLBI VAE1OS is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI VAE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TLBIVMALLE1OS, bit [18] when FEAT_TLBIOS is implemented:

Trap execution of TLBI VMALLE1OS at EL1 using AArch64 to EL2.

If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI VMALLE1OSNXS.

TLBIVMALLE1OSMeaning
0b0

Execution of TLBI VMALLE1OS is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI VMALLE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

ATS1E1WP, bit [17] when FEAT_PAN2 is implemented:

Trap execution of AT S1E1WP at EL1 using AArch64 to EL2.

ATS1E1WPMeaning
0b0

Execution of AT S1E1WP is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of AT S1E1WP at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

ATS1E1RP, bit [16] when FEAT_PAN2 is implemented:

Trap execution of AT S1E1RP at EL1 using AArch64 to EL2.

ATS1E1RPMeaning
0b0

Execution of AT S1E1RP is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of AT S1E1RP at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

ATS1E0W, bit [15]:

Trap execution of AT S1E0W at EL1 using AArch64 to EL2.

ATS1E0WMeaning
0b0

Execution of AT S1E0W is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of AT S1E0W at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

ATS1E0R, bit [14]:

Trap execution of AT S1E0R at EL1 using AArch64 to EL2.

ATS1E0RMeaning
0b0

Execution of AT S1E0R is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of AT S1E0R at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

ATS1E1W, bit [13]:

Trap execution of AT S1E1W at EL1 using AArch64 to EL2.

ATS1E1WMeaning
0b0

Execution of AT S1E1W is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of AT S1E1W at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

ATS1E1R, bit [12]:

Trap execution of AT S1E1R at EL1 using AArch64 to EL2.

ATS1E1RMeaning
0b0

Execution of AT S1E1R is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of AT S1E1R at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

DCZVA, bit [11]:

Trap execution of any of the following AArch64 instructions at EL1 and EL0 to EL2:

Unlike HCR_EL2.TDZ, this field has no effect on DCZID_EL0.DZP.

DCZVAMeaning
0b0

Execution of the specified instructions is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution at EL1 and EL0 using AArch64 of any of the specified instructions is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

DCCIVAC, bit [10]:

Trap execution of any of the following AArch64 instructions at EL1 and EL0 to EL2:

DCCIVACMeaning
0b0

Execution of the specified instructions is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then if the execution can be trapped, execution at EL1 and EL0 using AArch64 of any of the specified instructions is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

DCCVADP, bit [9] when FEAT_DPB2 is implemented:

Trap execution of any of the following AArch64 instructions at EL1 and EL0 to EL2:

DCCVADPMeaning
0b0

Execution of the specified instructions is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then if the execution can be trapped, execution at EL1 and EL0 using AArch64 of any of the specified instructions is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

DCCVAP, bit [8]:

Trap execution of any of the following AArch64 instructions at EL1 and EL0 to EL2:

DCCVAPMeaning
0b0

Execution of the specified instructions is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then if the execution can be trapped, execution at EL1 and EL0 using AArch64 of any of the specified instructions is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

DCCVAU, bit [7]:

Trap execution of DC CVAU at EL1 and EL0 using AArch64 to EL2.

DCCVAUMeaning
0b0

Execution of DC CVAU is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then if the execution can be trapped, execution of DC CVAU at EL1 and EL0 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

DCCISW, bit [6]:

Trap execution of any of the following AArch64 instructions at EL1 to EL2:

DCCISWMeaning
0b0

Execution of the specified instructions is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution at EL1 using AArch64 of any of the specified instructions is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

DCCSW, bit [5]:

Trap execution of any of the following AArch64 instructions at EL1 to EL2:

DCCSWMeaning
0b0

Execution of the specified instructions is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution at EL1 using AArch64 of any of the specified instructions is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

DCISW, bit [4]:

Trap execution of any of the following AArch64 instructions at EL1 to EL2:

DCISWMeaning
0b0

Execution of the specified instructions is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution at EL1 using AArch64 of any of the specified instructions is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

DCIVAC, bit [3]:

Trap execution of any of the following AArch64 instructions at EL1 to EL2:

DCIVACMeaning
0b0

Execution of the specified instructions is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then if the execution can be trapped, execution at EL1 using AArch64 of any of the specified instructions is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

ICIVAU, bit [2]:

Trap execution of IC IVAU at EL1 and EL0 using AArch64 to EL2.

ICIVAUMeaning
0b0

Execution of IC IVAU is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then if the execution can be trapped, execution of IC IVAU at EL1 and EL0 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

ICIALLU, bit [1]:

Trap execution of IC IALLU at EL1 using AArch64 to EL2.

ICIALLUMeaning
0b0

Execution of IC IALLU is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then if the execution can be trapped, execution of IC IALLU at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

ICIALLUIS, bit [0]:

Trap execution of IC IALLUIS at EL1 using AArch64 to EL2.

ICIALLUISMeaning
0b0

Execution of IC IALLUIS is not trapped by this mechanism.

0b1

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then if the execution can be trapped, execution of IC IALLUIS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

The reset behavior of this field is:

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, HFGITR_EL2

(op0 = 0b11, op1 = 0b100, CRn = 0b0001, CRm = 0b0001, op2 = 0b110)

if !(IsFeatureImplemented(FEAT_FGT) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR_EL3().FGTEn == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = NVMem(0x1C8); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().FGTEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = HFGITR_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = HFGITR_EL2(); end;

MSR HFGITR_EL2, <Xt>

(op0 = 0b11, op1 = 0b100, CRn = 0b0001, CRm = 0b0001, op2 = 0b110)

if !(IsFeatureImplemented(FEAT_FGT) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR_EL3().FGTEn == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem(0x1C8) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().FGTEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else HFGITR_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then HFGITR_EL2() = X{64}(t); end;

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