DC CIVAOC

Executing DC CIVAOC

If EL0 access is enabled, when executed at EL0, the instruction may generate a Permission fault, subject to the constraints described in 'MMU faults generated by cache maintenance operations'.

Execution of this instruction might require an address translation from VA to PA, and that translation might fault. For more information, see 'The data cache maintenance instruction (DC)'.

This system instruction is an alias of the SYS instruction.

Accesses to this instruction use the following encodings in the System instruction encoding space:

(op0 = 0b01, op1 = 0b011, CRn = 0b0111, CRm = 0b1111, op2 = 0b000)

if !(IsFeatureImplemented(FEAT_OCCMO) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif EffectivelyAtEL0NotInHost() then if SCTLR_EL1().UCI == '0' then AArch64_SystemAccessTraptoEL1orEL2(0x18); elsif EL2Enabled() && HCR_EL2().TPCP == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGITR_EL2().DCCIVAC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_DC(X{64}(t), CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_OuterCache); end; elsif EffectivelyAtEL0InHost() then if SCTLR_EL2().UCI == '0' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_DC(X{64}(t), CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_OuterCache); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().TPCP == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGITR_EL2().DCCIVAC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_DC(X{64}(t), CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_OuterCache); end; elsif PSTATE.EL == EL2 then AArch64_DC(X{64}(t), CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_OuterCache); elsif PSTATE.EL == EL3 then AArch64_DC(X{64}(t), CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_OuterCache); end;