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HCRX_EL2

Extended Hypervisor Configuration Register

Provides configuration controls for virtualization, including defining whether various operations are trapped to EL2.

Configuration

This register is present only when FEAT_HCX is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to HCRX_EL2 are UNDEFINED.

If EL2 is not implemented, this register is RES0 from EL3.

Attributes

HCRX_EL2 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0FNBVTLBIDOSEnNVnTTLBOSNVnTTLBISNVnTTLB
FDITRES0NVTGESRMASKEnVTLBIDEnPACMEnEnFPMGCSEnEnIDCP128EnSDERRTMEAEnSNERRD128EnPTTWISCTLR2EnTCR2EnRES0MSCEnMCE2CMOWVFNMIVINMITALLINTSMPMEFGTnXSFnXSEnASREnALSEnAS0

Bits [63:37]:

Reserved, RES0.

FNB, bit [36] when FEAT_TLBID is implemented:

This field, evaluated with HCR_EL2.FB, configures how TLBI and IC instructions are broadcast when executed from EL1.

For a description of the values derived by evaluating FB and FNB together, see HCR_EL2.FB.

The Effective value of this field is 0 if any of the following apply:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

The Effective value of this bit is 0.

Access to this field is RES0 .

VTLBIDOSEn, bit [35] when FEAT_TLBID is implemented:

Enable application of VTLBIDOS transformations.

This control applies to TLBI OS instructions executed at EL1.

VTLBIDOSEnMeaning
0b0

TLBI OS operations executed at EL1 are not transformed by VTLBIDOS<n>_EL2.

0b1

TLBI OS operations executed at EL1 are transformed by VTLBIDOS<n>_EL2.

The Effective value of this field is 0 if any of the following apply:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

NVnTTLBOS, bit [34] when FEAT_NV3 is implemented:

Nested Virtualization override of HCR_EL2.{TTLB, TTLBOS} for TLBI E1 instructions that specify the OS Shareability domain.

NVnTTLBOSMeaning
0b0

This control does not affect trapping of the specified instructions.

0b1

If NVHCR_EL2.TGE is 1, TLBI E1OS instructions that apply to stage 1 of the EL1&0 translation regime have their architected effect instead of being trapped by HCR_EL2.{TTLB, TTLBOS}.

If the Effective value of HCRX_EL2.NVTGE is 0, this field is ignored and has an Effective value of 0.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

NVnTTLBIS, bit [33] when FEAT_NV3 is implemented:

Nested Virtualization override of HCR_EL2.{TTLB, TTLBIS} for TLBI E1 instructions that specify the IS Shareability domain.

NVnTTLBISMeaning
0b0

This control does not affect trapping of the specified instructions.

0b1

If NVHCR_EL2.TGE is 1, TLBI E1IS instructions that apply to stage 1 of the EL1&0 translation regime have their architected effect instead of being trapped by HCR_EL2.{TTLB, TTLBIS}.

If the Effective value of HCRX_EL2.NVTGE is 0, this field is ignored and has an Effective value of 0.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

NVnTTLB, bit [32] when FEAT_NV3 is implemented:

Nested Virtualization override of HCR_EL2.TTLB for TLBI E1 instructions that do not specify an IS or OS Shareability domain.

NVnTTLBMeaning
0b0

This control does not affect trapping of the specified instructions.

0b1

If NVHCR_EL2.TGE is 1, TLBI E1 instructions that apply to stage 1 of the EL1&0 translation regime and do not specify an IS or OS Shareability domain have their architected effect instead of being trapped by HCR_EL2.TTLB.

If the Effective value of HCRX_EL2.NVTGE is 0, this field is ignored and has an Effective value of 0.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

FDIT, bit [31] when FEAT_FDIT is implemented:

Enforce data-independent timing for execution at EL1 and EL0.

FDITMeaning
0b0

This control does not affect data-independent timing of execution.

0b1

Data-independent timing of execution is enforced.

When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on execution.

The Effective value of this field is 0 when any of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

Bits [30:28]:

Reserved, RES0.

NVTGE, bit [27] when FEAT_NV3 is implemented:

Nested Virtualization Guest TGE behavior enable.

EL1 accesses to HCR_EL2 are redirected to NVHCR_EL2.

If FEAT_SRMASK2 is implemented, EL1 accesses to HCRX_EL2 are redirected to NVHCRX_EL2.

NVTGEMeaning
0b0

NVHCR_EL2.TGE is ignored and EL1 accesses to HCR_EL2 are not redirected to NVHCR_EL2.

0b1

EL1 accesses to HCR_EL2 are redirected to NVHCR_EL2 instead of being transformed to loads and stores. NVHCR_EL2.TGE is considered for ERET and TLBI traps.

If FEAT_SRMASK2 is implemented, EL1 accesses to HCRX_EL2 are redirected to NVHCRX_EL2 instead of being transformed to loads and stores.

This field has an Effective value of 0 if any of the following apply:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

SRMASKEn, bit [26] when FEAT_SRMASK is implemented:

If EL1 is using AArch64, accesses to the following registers are trapped to EL2 and reported using EC syndrome value 0x18:

SRMASKEnMeaning
0b0

EL1 accesses to the specified EL1 registers are trapped to EL2. The values in the registers are treated as 0.

0b1

This control does not cause any instructions to be trapped.

Traps generated by this control have a lower priority than traps generated by the HFGRTR2_EL2 and HFGWTR2_EL2 controls.

When EL2 is not implemented or not enabled in the current Security state, the Effective value of this field is 1.

Otherwise, when the Effective value of SCR_EL3.HXEn is 0, the Effective value of this field is 0.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

VTLBIDEn, bit [25] when FEAT_TLBID is implemented:

Enable application of VTLBID transformations.

This control applies to TLBI IS and IC IALLUIS instructions executed at EL1.

This control additionally applies to TLBI and IC IALLU instructions executed at EL1, if they apply to the Inner Shareable shareability domain as the result of HCR_EL2.FB configuration.

VTLBIDEnMeaning
0b0

TLBI operations executed at EL1 are not transformed by VTLBID<n>_EL2.

0b1

TLBI operations executed at EL1 are transformed by VTLBID<n>_EL2.

The Effective value of this field is 0 if any of the following apply:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

PACMEn, bit [24] when FEAT_PAuth_LR is implemented:

PACM Enable. Controls the effect of a PACM instruction at EL1 and EL0.

PACMEnMeaning
0b0

The effects of PACM are disabled at EL1 and EL0, regardless of the value in any other controls.

0b1

This control does not disable the effect of PACM at EL1 and EL0.

The Effective value of this field is 1 when any of the following are true:

The Effective value of this field is 0 when all of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

EnFPM, bit [23] when FEAT_FPMR is implemented:

Enables direct and indirect accesses to FPMR from EL0 and EL1.

When accesses to FPMR are disabled by this control:

EnFPMMeaning
0b0

Direct and indirect accesses to FPMR are disabled at EL1 and EL0.

0b1

This control does not cause any instructions to be trapped.

Traps are not taken if there is a higher priority exception generated by the access.

The Effective value of this field is 1 when any of the following are true:

The Effective value of this field is 0 when all of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

GCSEn, bit [22] when FEAT_GCS is implemented:

Guarded Control Stack enable. Controls Guarded Control Stack behavior at EL1 and EL0.

GCSEnMeaning
0b0

The Guarded Control Stack is disabled at EL1 and EL0.

0b1

Guarded Control Stack behavior at EL1 and EL0 is not affected by mechanism.

The Effective value of this field is 1 when any of the following are true:

The Effective value of this field is 0 when all of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

EnIDCP128, bit [21] when FEAT_SYSREG128 is implemented:

Enables access to IMPLEMENTATION DEFINED 128-bit System registers.

EnIDCP128Meaning
0b0

Accesses at EL1, EL0 to IMPLEMENTATION DEFINED 128-bit System registers are trapped to EL2 using EC syndrome value 0x14, unless the access generates a higher priority exception.

Disables the functionality of the 128-bit IMPLEMENTATION DEFINED System registers that are accessible at EL2.

0b1

No accesses are trapped by this control.

The Effective value of this field is 1 when any of the following are true:

The Effective value of this field is 0 when all of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

EnSDERR, bit [20] when FEAT_ADERR is implemented:

Enable Synchronous Device Read Error. Override SCTLR2_EL1.EnADERR.

EnSDERRMeaning
0b0

This field has no effect on External aborts on Device memory reads in the EL1&0 translation regime.

0b1

External abort on Device memory reads generate synchronous Data Abort exceptions in the EL1&0 translation regime.

Implementation-specific exceptions to applications of this field are described in 'Taking error exceptions'.

Setting this field to 1 does not guarantee that the PE is able to take a synchronous Data Abort exception for an External abort on a Device memory read in every case. There might be implementation-specific circumstances when an error on a load cannot be taken synchronously. These circumstances should be rare enough that treating such occurrences as fatal does not cause a significant increase in failure rate.

If FEAT_SVE is implemented, HCRX_EL2.EnSDERR is 1, and the access generating the External abort is due to any Active element of an SVE Non-fault vector load instruction or an Active element that is not the First active element of an SVE First-fault vector load instruction, then no exception is generated and the External abort is reported in the FFR.

Setting this field to 1 might have a performance impact for Device memory reads.

This field is ignored by the PE and has an Effective value of 0 when any of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

TMEA, bit [19] when FEAT_DoubleFault2 is implemented:

Trap Masked External Aborts. Controls whether a masked error exception at a lower Exception level is taken to EL2.

TMEAMeaning
0b0

Synchronous External abort exceptions, physical SError exceptions, and delegated SError exceptions at EL1 and EL0 are unaffected by this mechanism. That is, these exceptions are not taken to EL2 unless routed to EL2 by another control.

Virtual SError exceptions are not enabled by this mechanism.

0b1

When executing at Exception levels below EL2, if EL2 is enabled in the current Security state, then all of the following apply:

  • When PSTATE.A is 1, synchronous External abort exceptions are taken to EL2, unless they are routed to EL3.

  • Masked physical SError exceptions are taken to EL2, unless they are routed to EL3.

  • If FEAT_E3DSE is implemented, then masked delegated SError exceptions enabled by SCR_EL3.DSE are taken to EL2.

  • If HCR_EL2.TGE is 0, then virtual SError exceptions are enabled.

The Effective value of this field is 0 when any of the following are true:

Virtual SError exceptions are disabled when the Effective value of HCR_EL2.AMO is 0 and the Effective value of HCRX_EL2.TMEA is 0.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

EnSNERR, bit [18] when FEAT_ANERR is implemented:

Enable Synchronous Normal Read Error. Override SCTLR2_EL1.EnANERR.

EnSNERRMeaning
0b0

This field has no effect on External aborts on Normal memory reads in the EL1&0 translation regime.

0b1

External abort on Normal memory reads generate synchronous Data Abort exceptions in the EL1&0 translation regime.

Implementation-specific exceptions to applications of this field are described in 'Taking error exceptions'.

Setting this field to 1 does not guarantee that the PE is able to take a synchronous Data Abort exception for an External abort on a Normal memory read in every case. There might be implementation-specific circumstances when an error on a load cannot be taken synchronously. These circumstances should be rare enough that treating such occurrences as fatal does not cause a significant increase in failure rate.

If FEAT_SVE is implemented, HCRX_EL2.EnSNERR is 1, and the access generating the External abort is due to any Active element of an SVE Non-fault vector load instruction or an Active element that is not the First active element of an SVE First-fault vector load instruction, then no exception is generated and the External abort is reported in the FFR.

Setting this field to 1 might have a performance impact for Normal memory reads.

This field is ignored by the PE and has an Effective value of 0 when any of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

D128En, bit [17] when FEAT_D128 is implemented:

128-bit System Register trap control. Enable access to 128-bit System Registers that relate to VMSAv9-128 using MRRS, MSRR instructions.

If EL1 is using AArch64, accesses to the following registers are trapped to EL2 and reported using EC syndrome value 0x14:

D128EnMeaning
0b0

EL1 accesses to the specified registers are disabled, and trapped to EL2.

0b1

This control does not cause any instructions to be trapped.

When EL2 is not implemented or not enabled in the current Security state, the Effective value of this field is 1.

Otherwise, when the Effective value of SCR_EL3.HXEn is 0, the Effective value of this field is 0.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

PTTWI, bit [16] when FEAT_THE is implemented:

Permit Translation Table Walk Incoherence.

Permits RCWS instructions to generate writes that have the Reduced Coherence property.

PTTWIMeaning
0b0

Write accesses generated by RCWS at EL1 and EL0 do not have the Reduced Coherence property.

0b1

Write accesses generated by RCWS at EL1 and EL0 have the Reduced Coherence property, if enabled by TCR2_EL1.PTTWI.

The Effective value of this field is 1 when any of the following are true:

The Effective value of this field is 0 when all of the following are true:

This field is permitted to be cached in TLB.

This field is permitted to be implemented as a read-only field with a fixed value of 0.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

SCTLR2En, bit [15] when FEAT_SCTLR2 is implemented:

SCTLR2_EL1 Enable. In AArch64 state, accesses to SCTLR2_EL1 are trapped to EL2 and reported using EC syndrome value 0x18.

SCTLR2EnMeaning
0b0

Accesses to SCTLR2_EL1 at EL1 are trapped to EL2, unless the access generates a higher priority exception. The value in SCTLR2_EL1 is treated as 0.

0b1

This control does not cause any instructions to be trapped.

When EL2 is not implemented or not enabled in the current Security state, the Effective value of this field is 1.

Otherwise, when the Effective value of SCR_EL3.HXEn is 0, the Effective value of this field is 0.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

TCR2En, bit [14] when FEAT_TCR2 is implemented:

TCR2_EL1 Enable. In AArch64 state, accesses to TCR2_EL1 are trapped to EL2 and reported using EC syndrome value 0x18.

TCR2EnMeaning
0b0

Accesses to TCR2_EL1 at EL1 are trapped to EL2, unless the access generates a higher priority exception. The value in TCR2_EL1 is treated as 0.

0b1

This control does not cause any instructions to be trapped.

When EL2 is not implemented or not enabled in the current Security state, the Effective value of this field is 1.

Otherwise, when the Effective value of SCR_EL3.HXEn is 0, the Effective value of this field is 0.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

Bits [13:12]:

Reserved, RES0.

MSCEn, bit [11] when FEAT_MOPS is implemented:

Memory Set and Memory Copy instructions Enable. Enables execution of the CPY*, SETG*, SETP*, SETM*, and SETE* instructions at EL1 or EL0.

MSCEnMeaning
0b0

Execution of the Memory Copy and Memory Set instructions is UNDEFINED at EL1 or EL0.

0b1

This control does not cause any instructions to be UNDEFINED.

The Effective value of this field is 1 when any of the following are true:

The Effective value of this field is 0 when all of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

MCE2, bit [10] when FEAT_MOPS is implemented:

Controls Memory Copy and Memory Set exceptions generated as part of attempting to execute the Memory Copy and Memory Set instructions from EL1.

MCE2Meaning
0b0

Memory Copy and Memory Set exceptions generated from EL1 are taken to EL1.

0b1

Memory Copy and Memory Set exceptions generated from EL1 are taken to EL2.

The Effective value of this field is 0 when any of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

CMOW, bit [9] when FEAT_CMOW is implemented:

Controls the required permissions for the following cache maintenance instructions executed at EL1 or EL0:

CMOWMeaning
0b0

This control does not cause any instructions to generate a stage 2 Permission fault.

0b1

For these instructions, when executed at EL1 or EL0, the absence of stage 2 write permission generates a stage 2 permission fault.

For more information, see:

The Effective value of this field is 0 when any of the following are true:

This field is permitted to be cached in a TLB.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

VFNMI, bit [8] when FEAT_NMI is implemented:

Virtual FIQ Interrupt with Superpriority. Enables signaling of virtual FIQ interrupts with Superpriority.

VFNMIMeaning
0b0

When HCR_EL2.VF is 1, a signaled pending virtual FIQ interrupt does not have Superpriority.

0b1

When HCR_EL2.VF is 1, a signaled pending virtual FIQ interrupt has Superpriority.

When HCR_EL2.VF is 0, this field has no effect.

The Effective value of this field is 0 when any of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

VINMI, bit [7] when FEAT_NMI is implemented:

Virtual IRQ Interrupt with Superpriority. Enables signaling of virtual IRQ interrupts with Superpriority.

VINMIMeaning
0b0

When HCR_EL2.VI is 1, a signaled pending virtual IRQ interrupt does not have Superpriority.

0b1

When HCR_EL2.VI is 1, a signaled pending virtual IRQ interrupt has Superpriority.

When HCR_EL2.VI is 0, this field has no effect.

The Effective value of this field is 0 when any of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

TALLINT, bit [6] when FEAT_NMI is implemented:

Traps the following writes at EL1 using AArch64 to EL2, when EL2 is implemented and enabled:

TALLINTMeaning
0b0

This control does not cause any instructions to be trapped.

0b1

The specified MSR accesses at EL1 using AArch64 are trapped to EL2.

The Effective value of this field is 0 when any of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

SMPME, bit [5] when FEAT_SME is implemented:

Streaming Mode Priority Mapping Enable.

Controls mapping of the value of SMPRI_EL1.Priority for streaming execution priority at EL0 or EL1.

SMPMEMeaning
0b0

The effective priority value is taken from SMPRI_EL1.Priority.

0b1

The effective priority value is:

  • When the current Exception level is EL2 or EL3, the value of SMPRI_EL1.Priority.
  • When the current Exception level is EL0 or EL1, the value of the SMPRIMAP_EL2 field corresponding to the value of SMPRI_EL1.Priority.

When SMIDR_EL1.SMPS is '0', this field is RES0.

The Effective value of this field is 0 when any of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

FGTnXS, bit [4] when FEAT_XS is implemented:

Determines if the fine-grained traps in HFGITR_EL2 that apply to each of the TLBI maintenance instructions that are accessible at EL1 also apply to the corresponding TLBI maintenance instructions with the nXS qualifier.

FGTnXSMeaning
0b0

The fine-grained trap in the HFGITR_EL2 that applies to a TLBI maintenance instruction at EL1 also applies to the corresponding TLBI instruction with the nXS qualifier at EL1.

0b1

The fine-grained trap in the HFGITR_EL2 that applies to a TLBI maintenance instruction at EL1 does not apply to the corresponding TLBI instruction with the nXS qualifier at EL1.

The Effective value of this field is 0 when any of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

FnXS, bit [3] when FEAT_XS is implemented:

Determines the behavior of TLBI instructions affected by the XS attribute.

This control field also determines whether an AArch64 DSB instruction behaves as a DSB instruction with an nXS qualifier when executed at EL0 and EL1.

FnXSMeaning
0b0

This control does not have any effect on the behavior of the TLBI maintenance instructions.

0b1

A TLBI maintenance instruction without the nXS qualifier executed at EL1 behaves in the same way as the corresponding TLBI maintenance instruction with the nXS qualifier.

An AArch64 DSB instruction that applies to both loads and stores executed at EL1 or EL0 behaves in the same way as the corresponding DSB instruction with the nXS qualifier executed at EL1 or EL0.

The Effective value of this field is 0 when any of the following are true:

This field is permitted to be cached in a TLB.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

EnASR, bit [2] when FEAT_LS64_V is implemented:

When the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, traps execution of an ST64BV instruction at EL0 or EL1 to EL2.

EnASRMeaning
0b0

Execution of an ST64BV instruction at EL0 is trapped to EL2 if the execution is not trapped by SCTLR_EL1.EnASR.

Execution of an ST64BV instruction at EL1 is trapped to EL2.

0b1

This control does not cause any instructions to be trapped.

A trap of an ST64BV instruction is reported using EC syndrome value 0x0A, with an ISS code of 0x0000000.

The Effective value of this field is 1 when any of the following are true:

The Effective value of this field is 0 when all of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

EnALS, bit [1] when FEAT_LS64 is implemented:

When the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, traps execution of an LD64B or ST64B instruction at EL0 or EL1 to EL2.

EnALSMeaning
0b0

Execution of an LD64B or ST64B instruction at EL0 is trapped to EL2 if the execution is not trapped by SCTLR_EL1.EnALS.

Execution of an LD64B or ST64B instruction at EL1 is trapped to EL2.

0b1

This control does not cause any instructions to be trapped.

A trap of an LD64B or ST64B instruction is reported using EC syndrome value 0x0A, with an ISS code of 0x0000002.

The Effective value of this field is 1 when any of the following are true:

The Effective value of this field is 0 when all of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

EnAS0, bit [0] when FEAT_LS64_ACCDATA is implemented:

When the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, traps execution of an ST64BV0 instruction at EL0 or EL1 to EL2.

EnAS0Meaning
0b0

Execution of an ST64BV0 instruction at EL0 is trapped to EL2 if the execution is not trapped by SCTLR_EL1.EnAS0.

Execution of an ST64BV0 instruction at EL1 is trapped to EL2.

0b1

This control does not cause any instructions to be trapped.

A trap of an ST64BV0 instruction is reported using EC syndrome value 0x0A, with an ISS code of 0x0000001.

The Effective value of this field is 1 when any of the following are true:

The Effective value of this field is 0 when all of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, HCRX_EL2

(op0 = 0b11, op1 = 0b100, CRn = 0b0001, CRm = 0b0010, op2 = 0b010)

if !(IsFeatureImplemented(FEAT_HCX) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR_EL3().HXEn == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then if IsFeatureImplemented(FEAT_SRMASK2) && EffectiveHCRX_EL2_NVTGE() == '1' && (!HaveEL(EL3) || SCR2_EL3().SRMASK2En == '1') then X{64}(t) = NVHCRX_EL2(); else X{64}(t) = NVMem(0x0A0); end; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().HXEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = HCRX_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = HCRX_EL2(); end;

MSR HCRX_EL2, <Xt>

(op0 = 0b11, op1 = 0b100, CRn = 0b0001, CRm = 0b0010, op2 = 0b010)

if !(IsFeatureImplemented(FEAT_HCX) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR_EL3().HXEn == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then if IsFeatureImplemented(FEAT_SRMASK2) && EffectiveHCRX_EL2_NVTGE() == '1' && (!HaveEL(EL3) || SCR2_EL3().SRMASK2En == '1') then NVHCRX_EL2() = X{64}(t); else NVMem(0x0A0) = X{64}(t); end; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().HXEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else HCRX_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then HCRX_EL2() = X{64}(t); end;

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