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CPACRMASK_EL1

Architectural Feature Access Control Masking Register

Mask register to prevent updates of fields in CPACR_EL1 on writes to CPACR_EL1 or CPACRALIAS_EL1.

Configuration

This register is present only when FEAT_SRMASK is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to CPACRMASK_EL1 are UNDEFINED.

Attributes

CPACRMASK_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
TCPACTAME0POETTARES0SMENRES0FPENRES0ZENRES0

Bits [63:32]:

Reserved, RES0.

TCPAC, bit [31] when FEAT_NV2p1 is implemented:

Mask bit for TCPAC.

TCPACMeaning
0b0

CPACR_EL1.TCPAC is writable.

0b1

CPACR_EL1.TCPAC is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TAM, bit [30] when FEAT_AMUv1 is implemented and FEAT_NV2p1 is implemented:

Mask bit for TAM.

TAMMeaning
0b0

CPACR_EL1.TAM is writable.

0b1

CPACR_EL1.TAM is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

E0POE, bit [29] when FEAT_S1POE is implemented:

Mask bit for E0POE.

E0POEMeaning
0b0

CPACR_EL1.E0POE is writable.

0b1

CPACR_EL1.E0POE is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TTA, bit [28] when System register access to the trace unit registers is implemented:

Mask bit for TTA.

TTAMeaning
0b0

CPACR_EL1.TTA is writable.

0b1

CPACR_EL1.TTA is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Bits [27:25]:

Reserved, RES0.

SMEN, bit [24] when FEAT_SME is implemented:

Mask bit for SMEN.

SMENMeaning
0b0

CPACR_EL1.SMEN is writable.

0b1

CPACR_EL1.SMEN is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Bits [23:21]:

Reserved, RES0.

FPEN, bit [20]:

Mask bit for FPEN.

FPENMeaning
0b0

CPACR_EL1.FPEN is writable.

0b1

CPACR_EL1.FPEN is not writable.

The reset behavior of this field is:

Bits [19:17]:

Reserved, RES0.

ZEN, bit [16] when FEAT_SVE is implemented:

Mask bit for ZEN.

ZENMeaning
0b0

CPACR_EL1.ZEN is writable.

0b1

CPACR_EL1.ZEN is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Bits [15:0]:

Reserved, RES0.

Access Instructions

When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name CPACRMASK_EL1 or CPACRMASK_EL12 are not guaranteed to be ordered with respect to accesses using the other accessor name.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, CPACRMASK_EL1

(op0 = 0b11, op1 = 0b000, CRn = 0b0001, CRm = 0b0100, op2 = 0b010)

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGRTR2_EL2().nCPACRMASK_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().SRMASKEn == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x320); else X{64}(t) = CPACRMASK_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = CPTRMASK_EL2(); else X{64}(t) = CPACRMASK_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = CPACRMASK_EL1(); end;

MSR CPACRMASK_EL1, <Xt>

(op0 = 0b11, op1 = 0b000, CRn = 0b0001, CRm = 0b0100, op2 = 0b010)

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGWTR2_EL2().nCPACRMASK_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().SRMASKEn == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x320) = X{64}(t); elsif !IsZero(CPACRMASK_EL1()) then Undefined(); else CPACRMASK_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then if !IsZero(CPTRMASK_EL2()) then Undefined(); else CPTRMASK_EL2() = X{64}(t); end; else CPACRMASK_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then CPACRMASK_EL1() = X{64}(t); end;

When FEAT_VHE is implemented:

MRS <Xt>, CPACRMASK_EL12

(op0 = 0b11, op1 = 0b101, CRn = 0b0001, CRm = 0b0100, op2 = 0b010)

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then X{64}(t) = NVMem(0x320); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = CPACRMASK_EL1(); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X{64}(t) = CPACRMASK_EL1(); else Undefined(); end; end;

When FEAT_VHE is implemented:

MSR CPACRMASK_EL12, <Xt>

(op0 = 0b11, op1 = 0b101, CRn = 0b0001, CRm = 0b0100, op2 = 0b010)

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem(0x320) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else CPACRMASK_EL1() = X{64}(t); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then CPACRMASK_EL1() = X{64}(t); else Undefined(); end; end;

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