Architectural Feature Access Control Masking Register
This register is present only when FEAT_SRMASK is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to CPACRMASK_EL1 are UNDEFINED.
CPACRMASK_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| TCPAC | TAM | E0POE | TTA | RES0 | SMEN | RES0 | FPEN | RES0 | ZEN | RES0 | |||||||||||||||||||||
Reserved, RES0.
Mask bit for TCPAC.
| TCPAC | Meaning |
|---|---|
| 0b0 |
CPACR_EL1.TCPAC is writeable. |
| 0b1 |
CPACR_EL1.TCPAC is not writeable. |
The reset behavior of this field is:
Reserved, RES0.
Mask bit for TAM.
| TAM | Meaning |
|---|---|
| 0b0 |
CPACR_EL1.TAM is writeable. |
| 0b1 |
CPACR_EL1.TAM is not writeable. |
The reset behavior of this field is:
Reserved, RES0.
Mask bit for E0POE.
| E0POE | Meaning |
|---|---|
| 0b0 |
CPACR_EL1.E0POE is writeable. |
| 0b1 |
CPACR_EL1.E0POE is not writeable. |
The reset behavior of this field is:
Reserved, RES0.
Mask bit for TTA.
| TTA | Meaning |
|---|---|
| 0b0 |
CPACR_EL1.TTA is writeable. |
| 0b1 |
CPACR_EL1.TTA is not writeable. |
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Mask bit for SMEN.
| SMEN | Meaning |
|---|---|
| 0b0 |
CPACR_EL1.SMEN is writeable. |
| 0b1 |
CPACR_EL1.SMEN is not writeable. |
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Mask bit for FPEN.
| FPEN | Meaning |
|---|---|
| 0b0 |
CPACR_EL1.FPEN is writeable. |
| 0b1 |
CPACR_EL1.FPEN is not writeable. |
The reset behavior of this field is:
Reserved, RES0.
Mask bit for ZEN.
| ZEN | Meaning |
|---|---|
| 0b0 |
CPACR_EL1.ZEN is writeable. |
| 0b1 |
CPACR_EL1.ZEN is not writeable. |
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name CPACRMASK_EL1 or CPACRMASK_EL12 are not guaranteed to be ordered with respect to accesses using the other accessor name.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, CPACRMASK_EL1
(op0 = 0b11, op1 = 0b000, CRn = 0b0001, CRm = 0b0100, op2 = 0b010)
if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3.FGTEn2 == '0') || HFGRTR2_EL2.nCPACRMASK_EL1 == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2.SRMASKEn == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then X[t, 64] = NVMem[0x320]; else X[t, 64] = CPACRMASK_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif ELIsInHost(EL2) then X[t, 64] = CPTRMASK_EL2; else X[t, 64] = CPACRMASK_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = CPACRMASK_EL1;
MSR CPACRMASK_EL1, <Xt>
(op0 = 0b11, op1 = 0b000, CRn = 0b0001, CRm = 0b0100, op2 = 0b010)
if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3.FGTEn2 == '0') || HFGWTR2_EL2.nCPACRMASK_EL1 == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2.SRMASKEn == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem[0x320] = X[t, 64]; elsif !IsZero(EffectiveCPACRMASK_EL1()) then UNDEFINED; else CPACRMASK_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif ELIsInHost(EL2) then if !IsZero(EffectiveCPTRMASK_EL2()) then UNDEFINED; else CPTRMASK_EL2 = X[t, 64]; else CPACRMASK_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then CPACRMASK_EL1 = X[t, 64];
MRS <Xt>, CPACRMASK_EL12
(op0 = 0b11, op1 = 0b101, CRn = 0b0001, CRm = 0b0100, op2 = 0b010)
if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then X[t, 64] = NVMem[0x320]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = CPACRMASK_EL1; else UNDEFINED; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X[t, 64] = CPACRMASK_EL1; else UNDEFINED;
MSR CPACRMASK_EL12, <Xt>
(op0 = 0b11, op1 = 0b101, CRn = 0b0001, CRm = 0b0100, op2 = 0b010)
if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem[0x320] = X[t, 64]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else CPACRMASK_EL1 = X[t, 64]; else UNDEFINED; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then CPACRMASK_EL1 = X[t, 64]; else UNDEFINED;
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