Floating-point Mode Register
Controls behaviors of the FP8 instructions.
This register is present only when FEAT_FPMR is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to FPMR are UNDEFINED.
On entry to or exit from Streaming SVE mode, FPMR is set to 0.
This register is a Special-purpose register.
FPMR is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | LSCALE2 | ||||||||||||||||||||||||||||||
| NSCALE | RES0 | LSCALE | OSC | OSM | RES0 | F8D | F8S2 | F8S1 | |||||||||||||||||||||||
Reserved, RES0.
Downscaling value for instructions that convert the second FP8 input data stream to other floating-point formats.
This value is an unsigned integer that is subtracted from the result exponent.
The reset behavior of this field is:
Scaling value for instructions that convert other floating-point formats to an FP8 format.
This value is a signed integer that is added to the operand exponent.
The reset behavior of this field is:
Reserved, RES0.
Downscaling value.
This value is an unsigned integer that is subtracted from:
The product or the sum-of-products exponent, for multiplication instructions with FP8 operands.
The result exponent, for instructions that convert the first FP8 input data stream to other floating-point formats.
The reset behavior of this field is:
Overflow saturation for FP8 convert instructions. Specifies the result when a floating-point Overflow exception is detected.
| OSC | Meaning |
|---|---|
| 0b0 |
Infinity or NaN is generated. |
| 0b1 |
Maximum normal number is generated. |
The reset behavior of this field is:
Overflow saturation for FP8 multiplication instructions. Specifies the result when a floating-point Overflow exception is detected.
| OSM | Meaning |
|---|---|
| 0b0 |
Infinity is generated. |
| 0b1 |
Maximum normal number is generated. |
The reset behavior of this field is:
Reserved, RES0.
Destination result format for instructions that convert other floating-point values to an FP8 format.
| F8D | Meaning |
|---|---|
| 0b000 |
OFP8 E5M2 format. |
| 0b001 |
OFP8 E4M3 format. |
All other values are reserved.
Reserved values identify an unsupported format and behave as described in Reserved values in System and memory-mapped registers and translation table entries.
Additionally, FP8 instructions are permitted to set an FP8 result with an unsupported format to 0xFF and signal an Invalid Operation floating-point exception.
It is software's responsibility to check that a format value is supported in ID_AA64FPFR0_EL1[7:0], before writing it to this field.
For more information about the FP8 formats, see the OCP 8-bit Floating Point Specification (OFP8).
The reset behavior of this field is:
Second FP8 input data stream format for multiplication instructions with FP8 operands, and the corresponding instructions that convert an FP8 format to other floating-point formats.
| F8S2 | Meaning |
|---|---|
| 0b000 |
OFP8 E5M2 format. |
| 0b001 |
OFP8 E4M3 format. |
All other values are reserved.
Reserved values identify an unsupported format and behave as described in Reserved values in System and memory-mapped registers and translation table entries.
Additionally FP8 instructions are permitted to treat FP8 input values with an unsupported format as a signaling NaN.
It is software's responsibility to check that a format value is supported in ID_AA64FPFR0_EL1[7:0], before writing it to this field.
For more information about the FP8 formats, see the OCP 8-bit Floating Point Specification (OFP8).
The reset behavior of this field is:
First FP8 input data stream format for multiplication instructions with FP8 operands, and the corresponding instructions that convert an FP8 format to other floating-point formats.
| F8S1 | Meaning |
|---|---|
| 0b000 |
OFP8 E5M2 format. |
| 0b001 |
OFP8 E4M3 format. |
All other values are reserved.
Reserved values identify an unsupported format and behave as described in Reserved values in System and memory-mapped registers and translation table entries.
Additionally FP8 instructions are permitted to treat FP8 input values with an unsupported format as a signaling NaN.
It is software's responsibility to check that a format value is supported in ID_AA64FPFR0_EL1[7:0], before writing it to this field.
For more information about the FP8 formats, see the OCP 8-bit Floating Point Specification (OFP8).
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, FPMR
(op0 = 0b11, op1 = 0b011, CRn = 0b0100, CRm = 0b0100, op2 = 0b010)
if !(IsFeatureImplemented(FEAT_FPMR) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL != EL3 && EL3SDDUndefPriority() && SCR_EL3().EnFPM == '0' then Undefined(); elsif HaveEL(EL3) && PSTATE.EL != EL3 && EL3SDDUndefPriority() && CPTR_EL3().TFP == '1' then Undefined(); elsif PSTATE.EL == EL0 then if EffectivelyAtEL0NotInHost() && SCTLR_EL1().EnFPM == '0' then AArch64_SystemAccessTraptoEL1orEL2(0x18); elsif EffectivelyAtEL0InHost() && SCTLR_EL2().EnFPM == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && EffectivelyAtEL0NotInHost() && (!IsHCRXEL2Enabled() || HCRX_EL2().EnFPM == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().EnFPM == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectivelyAtEL0NotInHost() && CPACR_EL1().FPEN != '11' then if EL2Enabled() && EffectiveTGEforEL0Traps() == '1' then AArch64_SystemAccessTrap(EL2, 0x00); else AArch64_SystemAccessTrap(EL1, 0x07); end; elsif EffectivelyAtEL0InHost() && CPTR_EL2().FPEN != '11' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else X{64}(t) = FPMR(); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELIsInHost(EL0) && (!IsHCRXEL2Enabled() || HCRX_EL2().EnFPM == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().EnFPM == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif CPACR_EL1().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL1, 0x07); elsif EL2Enabled() && !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else X{64}(t) = FPMR(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().EnFPM == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else X{64}(t) = FPMR(); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().TFP == '1' then AArch64_SystemAccessTrap(EL3, 0x07); else X{64}(t) = FPMR(); end; end;
MSR FPMR, <Xt>
(op0 = 0b11, op1 = 0b011, CRn = 0b0100, CRm = 0b0100, op2 = 0b010)
if !(IsFeatureImplemented(FEAT_FPMR) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL != EL3 && EL3SDDUndefPriority() && SCR_EL3().EnFPM == '0' then Undefined(); elsif HaveEL(EL3) && PSTATE.EL != EL3 && EL3SDDUndefPriority() && CPTR_EL3().TFP == '1' then Undefined(); elsif PSTATE.EL == EL0 then if EffectivelyAtEL0NotInHost() && SCTLR_EL1().EnFPM == '0' then AArch64_SystemAccessTraptoEL1orEL2(0x18); elsif EffectivelyAtEL0InHost() && SCTLR_EL2().EnFPM == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && EffectivelyAtEL0NotInHost() && (!IsHCRXEL2Enabled() || HCRX_EL2().EnFPM == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().EnFPM == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectivelyAtEL0NotInHost() && CPACR_EL1().FPEN != '11' then if EL2Enabled() && EffectiveTGEforEL0Traps() == '1' then AArch64_SystemAccessTrap(EL2, 0x00); else AArch64_SystemAccessTrap(EL1, 0x07); end; elsif EffectivelyAtEL0InHost() && CPTR_EL2().FPEN != '11' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else FPMR() = X{64}(t); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELIsInHost(EL0) && (!IsHCRXEL2Enabled() || HCRX_EL2().EnFPM == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().EnFPM == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif CPACR_EL1().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL1, 0x07); elsif EL2Enabled() && !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else FPMR() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().EnFPM == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else FPMR() = X{64}(t); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().TFP == '1' then AArch64_SystemAccessTrap(EL3, 0x07); else FPMR() = X{64}(t); end; end;
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