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Nested Virtual Extended Hypervisor Configuration Register
Provides storage for a virtual view of HCRX_EL2 under nested virtualization.
Configuration
This register is present only when FEAT_NV3 is implemented, FEAT_SRMASK2 is implemented, and FEAT_AA64 is implemented. Otherwise, direct accesses to NVHCRX_EL2 are UNDEFINED.
Attributes
NVHCRX_EL2 is a 64-bit register.
Field descriptions
Bits [63:37]:
FNB, bit [36] when FEAT_TLBID is implemented:
Storage for the virtual view of HCRX_EL2.FNB under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.FNB == '1'.
Otherwise:
VTLBIDOSEn, bit [35] when FEAT_TLBID is implemented:
Storage for the virtual view of HCRX_EL2.VTLBIDOSEn under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.VTLBIDOSEn == '1'.
Otherwise:
NVnTTLBOS, bit [34] when FEAT_NV3 is implemented:
Storage for the virtual view of HCRX_EL2.NVnTTLBOS under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.NVnTTLBOS == '1'.
Otherwise:
NVnTTLBIS, bit [33] when FEAT_NV3 is implemented:
Storage for the virtual view of HCRX_EL2.NVnTTLBIS under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.NVnTTLBIS == '1'.
Otherwise:
NVnTTLB, bit [32] when FEAT_NV3 is implemented:
Storage for the virtual view of HCRX_EL2.NVnTTLB under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.NVnTTLB == '1'.
Otherwise:
FDIT, bit [31] when FEAT_FDIT is implemented:
Storage for the virtual view of HCRX_EL2.FDIT under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.FDIT == '1'.
Otherwise:
Bits [30:28]:
NVTGE, bit [27] when FEAT_NV3 is implemented:
Storage for the virtual view of HCRX_EL2.NVTGE under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.NVTGE == '1'.
Otherwise:
SRMASKEn, bit [26] when FEAT_SRMASK is implemented:
Storage for the virtual view of HCRX_EL2.SRMASKEn under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.SRMASKEn == '1'.
Otherwise:
VTLBIDEn, bit [25] when FEAT_TLBID is implemented:
Storage for the virtual view of HCRX_EL2.VTLBIDEn under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.VTLBIDEn == '1'.
Otherwise:
PACMEn, bit [24] when FEAT_PAuth_LR is implemented:
Storage for the virtual view of HCRX_EL2.PACMEn under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.PACMEn == '1'.
Otherwise:
EnFPM, bit [23] when FEAT_FPMR is implemented:
Storage for the virtual view of HCRX_EL2.EnFPM under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.EnFPM == '1'.
Otherwise:
GCSEn, bit [22] when FEAT_GCS is implemented:
Storage for the virtual view of HCRX_EL2.GCSEn under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.GCSEn == '1'.
Otherwise:
EnIDCP128, bit [21] when FEAT_SYSREG128 is implemented:
Storage for the virtual view of HCRX_EL2.EnIDCP128 under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.EnIDCP128 == '1'.
Otherwise:
EnSDERR, bit [20] when FEAT_ADERR is implemented:
Storage for the virtual view of HCRX_EL2.EnSDERR under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.EnSDERR == '1'.
Otherwise:
TMEA, bit [19] when FEAT_DoubleFault2 is implemented:
Storage for the virtual view of HCRX_EL2.TMEA under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.TMEA == '1'.
Otherwise:
EnSNERR, bit [18] when FEAT_ANERR is implemented:
Storage for the virtual view of HCRX_EL2.EnSNERR under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.EnSNERR == '1'.
Otherwise:
D128En, bit [17] when FEAT_D128 is implemented:
Storage for the virtual view of HCRX_EL2.D128En under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.D128En == '1'.
Otherwise:
PTTWI, bit [16] when FEAT_THE is implemented:
Storage for the virtual view of HCRX_EL2.PTTWI under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.PTTWI == '1'.
Otherwise:
SCTLR2En, bit [15] when FEAT_SCTLR2 is implemented:
Storage for the virtual view of HCRX_EL2.SCTLR2En under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.SCTLR2En == '1'.
Otherwise:
TCR2En, bit [14] when FEAT_TCR2 is implemented:
Storage for the virtual view of HCRX_EL2.TCR2En under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.TCR2En == '1'.
Otherwise:
Bits [13:12]:
MSCEn, bit [11] when FEAT_MOPS is implemented:
Storage for the virtual view of HCRX_EL2.MSCEn under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.MSCEn == '1'.
Otherwise:
MCE2, bit [10] when FEAT_MOPS is implemented:
Storage for the virtual view of HCRX_EL2.MCE2 under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.MCE2 == '1'.
Otherwise:
CMOW, bit [9] when FEAT_CMOW is implemented:
Storage for the virtual view of HCRX_EL2.CMOW under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.CMOW == '1'.
Otherwise:
VFNMI, bit [8] when FEAT_NMI is implemented:
Storage for the virtual view of HCRX_EL2.VFNMI under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.VFNMI == '1'.
Otherwise:
VINMI, bit [7] when FEAT_NMI is implemented:
Storage for the virtual view of HCRX_EL2.VINMI under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.VINMI == '1'.
Otherwise:
TALLINT, bit [6] when FEAT_NMI is implemented:
Storage for the virtual view of HCRX_EL2.TALLINT under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.TALLINT == '1'.
Otherwise:
SMPME, bit [5] when FEAT_SME is implemented:
Storage for the virtual view of HCRX_EL2.SMPME under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.SMPME == '1'.
Otherwise:
FGTnXS, bit [4] when FEAT_XS is implemented:
Storage for the virtual view of HCRX_EL2.FGTnXS under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.FGTnXS == '1'.
Otherwise:
FnXS, bit [3] when FEAT_XS is implemented:
Storage for the virtual view of HCRX_EL2.FnXS under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.FnXS == '1'.
Otherwise:
EnASR, bit [2] when FEAT_LS64_V is implemented:
Storage for the virtual view of HCRX_EL2.EnASR under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.EnASR == '1'.
Otherwise:
EnALS, bit [1] when FEAT_LS64 is implemented:
Storage for the virtual view of HCRX_EL2.EnALS under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.EnALS == '1'.
Otherwise:
EnAS0, bit [0] when FEAT_LS64_ACCDATA is implemented:
Storage for the virtual view of HCRX_EL2.EnAS0 under nested virtualization.
The reset behavior of this field is:
- On a Warm reset,
this field resets
to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
- Access to this field is RO if all the following are true:
- FEAT_SRMASK2 is implemented.
- EL1 is the current Exception level.
- EL3 is not implemented or SCR2_EL3.SRMASK2En == '1'.
- NVHCRXMASK_EL2.EnAS0 == '1'.
Otherwise:
Access Instructions
Accesses to this register use the following encodings in the System register encoding space:
(op0 = 0b11, op1 = 0b100, CRn = 0b0001, CRm = 0b0101, op2 = 0b001)
if !(IsFeatureImplemented(FEAT_NV3) && IsFeatureImplemented(FEAT_SRMASK2) && IsFeatureImplemented(FEAT_AA64)) then
Undefined();
elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR2_EL3().SRMASK2En == '0' then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if IsFeatureImplemented(FEAT_NV3) && EffectiveHCRX_EL2_NVTGE() == '1' then
X{64}(t) = NVMem(0x0A0);
elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then
AArch64_SystemAccessTrap(EL2, 0x18);
else
Undefined();
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && IsFeatureImplemented(FEAT_SCR2) && SCR2_EL3().SRMASK2En == '0' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
else
X{64}(t) = NVHCRX_EL2();
end;
elsif PSTATE.EL == EL3 then
X{64}(t) = NVHCRX_EL2();
end;
(op0 = 0b11, op1 = 0b100, CRn = 0b0001, CRm = 0b0101, op2 = 0b001)
if !(IsFeatureImplemented(FEAT_NV3) && IsFeatureImplemented(FEAT_SRMASK2) && IsFeatureImplemented(FEAT_AA64)) then
Undefined();
elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR2_EL3().SRMASK2En == '0' then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if IsFeatureImplemented(FEAT_NV3) && EffectiveHCRX_EL2_NVTGE() == '1' then
NVMem(0x0A0) = X{64}(t);
elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then
AArch64_SystemAccessTrap(EL2, 0x18);
else
Undefined();
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && IsFeatureImplemented(FEAT_SCR2) && SCR2_EL3().SRMASK2En == '0' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
else
NVHCRX_EL2() = X{64}(t);
end;
elsif PSTATE.EL == EL3 then
NVHCRX_EL2() = X{64}(t);
end;
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