VTLBID<n>_EL2 | Jon's Arm Reference

This register is present only when FEAT_TLBID is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to VTLBID<n>_EL2 are UNDEFINED.

The number of implemented registers, and number of TD fields depends on the values of TLBIDIDR_EL1.{NIS, NVIS} as follows:

Attributes

Field descriptions

When UInt(TLBIDIDR_EL1.NIS) <= 8:

TD<m>, bits [8m+7:8m], for m = 7 to 0:

NIS	NVIS	Outcome
0	0	None of VTLBID<n>_EL2 are implemented.
0	> 0	Prohibited.
x	0	1 TD<m> field, in 1 VTLBID<n>_EL2 register.
<= 8	1	2 TD<m> fields, in 1 VTLBID<n>_EL2 register.
<= 8	2	4 TD<m> fields, in 1 VTLBID<n>_EL2 register.
<= 8	3	8 TD<m> fields, in 1 VTLBID<n>_EL2 register.
<= 8	4	16 TD<m> fields, across 2 VTLBID<n>_EL2 registers.
<= 8	5	32 TD<m> fields, across 4 VTLBID<n>_EL2 registers.
> 8	1	2 TD<m> fields, in 1 VTLBID<n>_EL2 register.
> 8	2	4 TD<m> fields, in 1 VTLBID<n>_EL2 register.
> 8	3	8 TD<m> fields, across 2 VTLBID<n>_EL2 registers.
> 8	4	16 TD<m> fields, across 4 VTLBID<n>_EL2 registers.

Virtual to physical TLBID transformation when TLBIDIDR_EL1.NIS <= 8.

This 8-bit field indicates which physical TLBI Domain corresponds to the EL1 view of one virtual TLBI Domain.

For this field, VTLBID<n>_EL2.TD<m> then:

This field describes the physical TLBI Domain that corresponds to the EL1 view of domain t, where n is t / 8 and m is t % 8.

Bits of this field above the size shown in TLBIDIDR_EL1.NIS are RES0.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

When UInt(TLBIDIDR_EL1.NIS) >= 9:

TD<m>, bits [16m+15:16m], for m = 3 to 0:

Virtual to physical TLBID transformation when TLBIDIDR_EL1.NIS > 8.

This 16-bit field indicates which physical TLBI Domain corresponds to the EL1 view of one virtual TLBI Domain.

For this field, VTLBID<n>_EL2.TD<m> then:

This field describes the physical TLBI Domain that corresponds to the EL1 view of domain t, where n is t / 4 and m is t % 4.

Bits of this field above the size shown in TLBIDIDR_EL1.NIS are RES0.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, VTLBID<n>_EL2 ; Where n = 0-3

(op0 = 0b11, op1 = 0b100, CRn = 0b0010, CRm = 0b1000, op2 = 0b0:n[1:0])

let n:integer = UInt(op2[1:0]); if !(IsFeatureImplemented(FEAT_TLBID) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif n >= NUM_VTLBID_REGS then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR_EL3().VTLBIDEn == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = NVMem(0x520 + (8 * n)); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().VTLBIDEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = VTLBID_EL2(n); end; elsif PSTATE.EL == EL3 then X{64}(t) = VTLBID_EL2(n); end;

MSR VTLBID<n>_EL2, <Xt> ; Where n = 0-3

(op0 = 0b11, op1 = 0b100, CRn = 0b0010, CRm = 0b1000, op2 = 0b0:n[1:0])

let n:integer = UInt(op2[1:0]); if !(IsFeatureImplemented(FEAT_TLBID) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif n >= NUM_VTLBID_REGS then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR_EL3().VTLBIDEn == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem(0x520 + (8 * n)) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().VTLBIDEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else VTLBID_EL2(n) = X{64}(t); end; elsif PSTATE.EL == EL3 then VTLBID_EL2(n) = X{64}(t); end;

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TD7								TD6								TD5								TD4
TD3								TD2								TD1								TD0

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TD3																TD2
TD1																TD0

VTLBID<n>_EL2, n = 0 - 3

Configuration

Attributes

Field descriptions

When UInt(TLBIDIDR_EL1.NIS) <= 8:

TD<m>, bits [8m+7:8m], for m = 7 to 0:

When UInt(TLBIDIDR_EL1.NIS) >= 9:

TD<m>, bits [16m+15:16m], for m = 3 to 0:

Access Instructions

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TD7								TD6								TD5								TD4
TD3								TD2								TD1								TD0

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TD3																TD2
TD1																TD0

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TD7								TD6								TD5								TD4
TD3								TD2								TD1								TD0

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
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TD3																TD2
TD1																TD0

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TD7								TD6								TD5								TD4
TD3								TD2								TD1								TD0

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TD3																TD2
TD1																TD0