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TCR2MASK_EL1

Extended Translation Control Masking Register (EL1)

Mask register to prevent updates of fields in TCR2_EL1 on writes to TCR2_EL1 or TCR2ALIAS_EL1.

Configuration

This register is present only when FEAT_SRMASK is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to TCR2MASK_EL1 are UNDEFINED.

Attributes

TCR2MASK_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0FNGNA1FNGNA0RES0FNG1FNG0A2DisCH1DisCH0RES0HAFTPTTWIRES0D128AIEPOEE0POEPIEPnCH

Bits [63:22]:

Reserved, RES0.

FNGNA1, bit [21] when FEAT_THE is implemented:

Mask bit for FNGNA1.

FNGNA1Meaning
0b0

TCR2_EL1.FNGNA1 is writeable.

0b1

TCR2_EL1.FNGNA1 is not writeable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

FNGNA0, bit [20] when FEAT_THE is implemented:

Mask bit for FNGNA0.

FNGNA0Meaning
0b0

TCR2_EL1.FNGNA0 is writeable.

0b1

TCR2_EL1.FNGNA0 is not writeable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Bit [19]:

Reserved, RES0.

FNG1, bit [18] when FEAT_ASID2 is implemented:

Mask bit for FNG1.

FNG1Meaning
0b0

TCR2_EL1.FNG1 is writeable.

0b1

TCR2_EL1.FNG1 is not writeable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

FNG0, bit [17] when FEAT_ASID2 is implemented:

Mask bit for FNG0.

FNG0Meaning
0b0

TCR2_EL1.FNG0 is writeable.

0b1

TCR2_EL1.FNG0 is not writeable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

A2, bit [16] when FEAT_ASID2 is implemented:

Mask bit for A2.

A2Meaning
0b0

TCR2_EL1.A2 is writeable.

0b1

TCR2_EL1.A2 is not writeable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

DisCH1, bit [15] when FEAT_D128 is implemented:

Mask bit for DisCH1.

DisCH1Meaning
0b0

TCR2_EL1.DisCH1 is writeable.

0b1

TCR2_EL1.DisCH1 is not writeable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

DisCH0, bit [14] when FEAT_D128 is implemented:

Mask bit for DisCH0.

DisCH0Meaning
0b0

TCR2_EL1.DisCH0 is writeable.

0b1

TCR2_EL1.DisCH0 is not writeable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Bits [13:12]:

Reserved, RES0.

HAFT, bit [11] when FEAT_HAFT is implemented:

Mask bit for HAFT.

HAFTMeaning
0b0

TCR2_EL1.HAFT is writeable.

0b1

TCR2_EL1.HAFT is not writeable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

PTTWI, bit [10] when FEAT_THE is implemented:

Mask bit for PTTWI.

PTTWIMeaning
0b0

TCR2_EL1.PTTWI is writeable.

0b1

TCR2_EL1.PTTWI is not writeable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Bits [9:6]:

Reserved, RES0.

D128, bit [5] when FEAT_D128 is implemented:

Mask bit for D128.

D128Meaning
0b0

TCR2_EL1.D128 is writeable.

0b1

TCR2_EL1.D128 is not writeable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

AIE, bit [4] when FEAT_AIE is implemented:

Mask bit for AIE.

AIEMeaning
0b0

TCR2_EL1.AIE is writeable.

0b1

TCR2_EL1.AIE is not writeable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

POE, bit [3] when FEAT_S1POE is implemented:

Mask bit for POE.

POEMeaning
0b0

TCR2_EL1.POE is writeable.

0b1

TCR2_EL1.POE is not writeable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

E0POE, bit [2] when FEAT_S1POE is implemented:

Mask bit for E0POE.

E0POEMeaning
0b0

TCR2_EL1.E0POE is writeable.

0b1

TCR2_EL1.E0POE is not writeable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

PIE, bit [1] when FEAT_S1PIE is implemented:

Mask bit for PIE.

PIEMeaning
0b0

TCR2_EL1.PIE is writeable.

0b1

TCR2_EL1.PIE is not writeable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

PnCH, bit [0] when FEAT_THE is implemented:

Mask bit for PnCH.

PnCHMeaning
0b0

TCR2_EL1.PnCH is writeable.

0b1

TCR2_EL1.PnCH is not writeable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Access Instructions

When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name TCR2MASK_EL1 or TCR2MASK_EL12 are not guaranteed to be ordered with respect to accesses using the other accessor name.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, TCR2MASK_EL1

(op0 = 0b11, op1 = 0b000, CRn = 0b0010, CRm = 0b0111, op2 = 0b011)

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3.FGTEn2 == '0') || HFGRTR2_EL2.nTCR2MASK_EL1 == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2.SRMASKEn == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then X[t, 64] = NVMem[0x338]; else X[t, 64] = TCR2MASK_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif ELIsInHost(EL2) then X[t, 64] = TCR2MASK_EL2; else X[t, 64] = TCR2MASK_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = TCR2MASK_EL1;

MSR TCR2MASK_EL1, <Xt>

(op0 = 0b11, op1 = 0b000, CRn = 0b0010, CRm = 0b0111, op2 = 0b011)

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3.FGTEn2 == '0') || HFGWTR2_EL2.nTCR2MASK_EL1 == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2.SRMASKEn == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem[0x338] = X[t, 64]; elsif !IsZero(EffectiveTCR2MASK_EL1()) then UNDEFINED; else TCR2MASK_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif ELIsInHost(EL2) then if !IsZero(EffectiveTCR2MASK_EL2()) then UNDEFINED; else TCR2MASK_EL2 = X[t, 64]; else TCR2MASK_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then TCR2MASK_EL1 = X[t, 64];

MRS <Xt>, TCR2MASK_EL12

(op0 = 0b11, op1 = 0b101, CRn = 0b0010, CRm = 0b0111, op2 = 0b011)

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then X[t, 64] = NVMem[0x338]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = TCR2MASK_EL1; else UNDEFINED; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X[t, 64] = TCR2MASK_EL1; else UNDEFINED;

MSR TCR2MASK_EL12, <Xt>

(op0 = 0b11, op1 = 0b101, CRn = 0b0010, CRm = 0b0111, op2 = 0b011)

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem[0x338] = X[t, 64]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else TCR2MASK_EL1 = X[t, 64]; else UNDEFINED; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then TCR2MASK_EL1 = X[t, 64]; else UNDEFINED;

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