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VTLBIDOS<n>_EL2, n = 0 - 3

Virtual TLBI Domain Outer Shareable Registers

Transform the value of TLBID in TLBI OS operations executed at EL1 before the operation is broadcast.

Configuration

This register is present only when FEAT_TLBID is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to VTLBIDOS<n>_EL2 are UNDEFINED.

The number of implemented registers, and the number of TD fields depends on the values of TLBIDIDR_EL1.{NOS, NVOS} as follows:

NOSNVOSOutcome
00None of VTLBIDOS<n>_EL2 are implemented.
0> 0Prohibited.
> 001 TD<m> field, in 1 VTLBIDOS<n>_EL2 register.
<= 812 TD<m> fields, in 1 VTLBIDOS<n>_EL2 register.
<= 824 TD<m> fields, in 1 VTLBIDOS<n>_EL2 register.
<= 838 TD<m> fields, in 1 VTLBIDOS<n>_EL2 register.
<= 8416 TD<m> fields, across 2 VTLBIDOS<n>_EL2 registers.
<= 8532 TD<m> fields, across 4 VTLBIDOS<n>_EL2 registers.
> 812 TD<m> fields, in 1 VTLBIDOS<n>_EL2 register.
> 824 TD<m> fields, in 1 VTLBIDOS<n>_EL2 register.
> 838 TD<m> fields, across 2 VTLBIDOS<n>_EL2 registers.
> 8416 TD<m> fields, across 4 VTLBIDOS<n>_EL2 registers.

If EL2 is not implemented, this register is RES0 from EL3.

Attributes

VTLBIDOS<n>_EL2 is a 64-bit register.

Field descriptions

When UInt(TLBIDIDR_EL1.NOS) <= 8:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
TD7TD6TD5TD4
TD3TD2TD1TD0

TD<m>, bits [8m+7:8m], for m = 7 to 0:

Virtual to physical TLBID transformation for Outer shareable TLBIs when TLBIDIDR_EL1.NOS <= 8.

This 8-bit field indicates which physical TLBI Domain corresponds to the EL1 view of one virtual TLBI Domain for TLBI OS instructions.

For VTLBIDOS<n>_EL2.TD<m> this field describes the physical TLBI Domain that corresponds to the EL1 view of domain t, where n is t / 8 and m is t mod 8.

Bits of this field above the size shown in TLBIDIDR_EL1.NOS are RES0.

The reset behavior of this field is:

When UInt(TLBIDIDR_EL1.NOS) >= 9:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
TD3TD2
TD1TD0

TD<m>, bits [16m+15:16m], for m = 3 to 0:

Virtual to physical TLBID transformation for Outer shareable TLBIs when TLBIDIDR_EL1.NOS > 8.

This 16-bit field indicates which physical TLBI Domain corresponds to the EL1 view of one virtual TLBI Domain for TLBI OS instructions.

For VTLBIDOS<n>_EL2.TD<m> this field describes the physical TLBI Domain that corresponds to the EL1 view of domain t, where n is t / 4 and m is t mod 4.

Bits of this field above the size shown in TLBIDIDR_EL1.NOS are RES0.

The reset behavior of this field is:

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, VTLBIDOS<n>_EL2 ; Where n = 0-3

(op0 = 0b11, op1 = 0b100, CRn = 0b0010, CRm = 0b1001, op2 = 0b0:n[1:0])

let n:integer = UInt(op2[1:0]); if !(IsFeatureImplemented(FEAT_TLBID) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif n >= NUM_VTLBID_REGS then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR_EL3().VTLBIDEn == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = NVMem(0x540 + (8 * n)); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().VTLBIDEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = VTLBIDOS_EL2(n); end; elsif PSTATE.EL == EL3 then X{64}(t) = VTLBIDOS_EL2(n); end;

MSR VTLBIDOS<n>_EL2, <Xt> ; Where n = 0-3

(op0 = 0b11, op1 = 0b100, CRn = 0b0010, CRm = 0b1001, op2 = 0b0:n[1:0])

let n:integer = UInt(op2[1:0]); if !(IsFeatureImplemented(FEAT_TLBID) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif n >= NUM_VTLBID_REGS then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR_EL3().VTLBIDEn == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem(0x540 + (8 * n)) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().VTLBIDEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else VTLBIDOS_EL2(n) = X{64}(t); end; elsif PSTATE.EL == EL3 then VTLBIDOS_EL2(n) = X{64}(t); end;

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