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DC GVA: Data Cache set Allocation Tag by VA

Purpose

Write a value to the Allocation Tags of a naturally aligned block of N bytes, where the size of N is identified in DCZID_EL0. The Allocation Tag used is determined by the input address.

Configuration

This instruction is present only when FEAT_MTE is implemented. Otherwise, direct accesses to DC GVA are UNDEFINED.

Attributes

DC GVA is a 64-bit System instruction.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
VA
VA

VA, bits [63:0]

Virtual address to use. There is no alignment restriction on the address within the block of N bytes that is used.

Executing DC GVA

When this instruction is executed, it can generate memory faults or watchpoints which are prioritized in the same way as other memory-related faults or watchpoints. If a synchronous Data Abort fault or a watchpoint is generated, the CM bit in the ESR_ELx.ISS field is not set.

A DC GVA instruction to any type of Device memory is CONSTRAINED UNPREDICTABLE between:

This instruction applies to Normal memory regardless of cacheability attributes.

This instruction behaves as a set of stores to each Allocation Tag within the block being accessed, and so it:

Accesses to this instruction use the following encodings in the System instruction encoding space:

DC GVA, <Xt>

op0op1CRnCRmop2
0b010b0110b01110b01000b011

if !IsFeatureImplemented(FEAT_MTE) then UNDEFINED; elsif PSTATE.EL == EL0 then if !ELIsInHost(EL0) && SCTLR_EL1.DZE == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && HCR_EL2.TDZ == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.DCZVA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL0) && SCTLR_EL2.DZE == '0' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.MemZero(X[t, 64], CacheType_Tag); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TDZ == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.DCZVA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.MemZero(X[t, 64], CacheType_Tag); elsif PSTATE.EL == EL2 then AArch64.MemZero(X[t, 64], CacheType_Tag); elsif PSTATE.EL == EL3 then AArch64.MemZero(X[t, 64], CacheType_Tag);