Instruction Cache line Invalidate by VA to PoU
Invalidate instruction cache by address to Point of Unification.
AArch64 System instruction IC IVAU performs the same function as AArch32 System instruction ICIMVAU.
This instruction is present only when FEAT_AA64 is implemented. Otherwise, direct accesses to IC IVAU are UNDEFINED.
IC IVAU is a 64-bit System instruction.
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Virtual address to use. No alignment restrictions apply to this VA.
If EL0 access is enabled, when executed at EL0, the instruction may generate a Permission fault, subject to the constraints described in 'MMU faults generated by cache maintenance operations'.
Execution of this instruction might require an address translation from VA to PA, and that translation might fault. For more information, see 'The instruction cache maintenance instruction (IC)'.
This system instruction is an alias of the SYS instruction.
Accesses to this instruction use the following encodings in the System instruction encoding space:
IC IVAU{, <Xt>}
(op0 = 0b01, op1 = 0b011, CRn = 0b0111, CRm = 0b0101, op2 = 0b001)
if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif EffectivelyAtEL0NotInHost() then if !AArch64_CanTrapIC(CacheType_Instruction, CacheOp_Invalidate, CacheOpScope_PoU) then ExecuteAsNOP(); elsif SCTLR_EL1().UCI == '0' then AArch64_SystemAccessTraptoEL1orEL2(0x18); elsif EL2Enabled() && HCR_EL2().TPU == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().TOCU == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGITR_EL2().ICIVAU == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else if AArch64_TreatICAsNOP(CacheType_Instruction, CacheOp_Invalidate, CacheOpScope_PoU) then ExecuteAsNOP(); else AArch64_IC(X{64}(t), CacheOpScope_PoU); end; end; elsif EffectivelyAtEL0InHost() then if !AArch64_CanTrapIC(CacheType_Instruction, CacheOp_Invalidate, CacheOpScope_PoU) then ExecuteAsNOP(); elsif SCTLR_EL2().UCI == '0' then AArch64_SystemAccessTrap(EL2, 0x18); else if AArch64_TreatICAsNOP(CacheType_Instruction, CacheOp_Invalidate, CacheOpScope_PoU) then ExecuteAsNOP(); else AArch64_IC(X{64}(t), CacheOpScope_PoU); end; end; elsif PSTATE.EL == EL1 then if !AArch64_CanTrapIC(CacheType_Instruction, CacheOp_Invalidate, CacheOpScope_PoU) then ExecuteAsNOP(); elsif EL2Enabled() && HCR_EL2().TPU == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().TOCU == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGITR_EL2().ICIVAU == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else if AArch64_TreatICAsNOP(CacheType_Instruction, CacheOp_Invalidate, CacheOpScope_PoU) then ExecuteAsNOP(); else AArch64_IC(X{64}(t), CacheOpScope_PoU); end; end; elsif PSTATE.EL == EL2 then if !AArch64_CanTrapIC(CacheType_Instruction, CacheOp_Invalidate, CacheOpScope_PoU) then ExecuteAsNOP(); else if AArch64_TreatICAsNOP(CacheType_Instruction, CacheOp_Invalidate, CacheOpScope_PoU) then ExecuteAsNOP(); else AArch64_IC(X{64}(t), CacheOpScope_PoU); end; end; elsif PSTATE.EL == EL3 then if AArch64_TreatICAsNOP(CacheType_Instruction, CacheOp_Invalidate, CacheOpScope_PoU) then ExecuteAsNOP(); else AArch64_IC(X{64}(t), CacheOpScope_PoU); end; end;
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