Secure Configuration Register
Defines the configuration of the current Security state.
This register is present only when FEAT_SCR2 is implemented, EL3 is implemented, and FEAT_AA64 is implemented. Otherwise, direct accesses to SCR2_EL3 are UNDEFINED.
SCR2_EL3 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | SRMASK2En | NV3En | FDIT | ||||||||||||||||||||||||||||
Reserved, RES0.
Enables access to the following registers:
| SRMASK2En | Meaning |
|---|---|
| 0b0 |
EL2 accesses to the specified registers are trapped to EL3. |
| 0b1 |
No accesses are trapped by this mechanism. |
Traps are reported using EC syndrome value 0x18.
When EL3 is not implemented, the Effective value of this field is 1.
The reset behavior of this field is:
Reserved, RES0.
Enables access to the NVHCR_EL2 register at EL2.
| NV3En | Meaning |
|---|---|
| 0b0 |
EL2 accesses to the specified register is trapped to EL3. The Effective value of HCRX_EL2.NVTGE is 0. |
| 0b1 |
No accesses are trapped by this mechanism. |
Access to NVHCR_EL2 is trapped to EL3 and reported using EC syndrome value 0x18.
When EL3 is not implemented, the Effective value of this field is 1.
The reset behavior of this field is:
Reserved, RES0.
Enforce data-independent timing for execution at EL2, EL1 and EL0.
| FDIT | Meaning |
|---|---|
| 0b0 |
This control does not affect data-independent timing of execution. |
| 0b1 |
Data-independent timing of execution is enforced. |
When EL3 is not implemented, the Effective value of this field is 0.
The reset behavior of this field is:
Reserved, RES0.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, SCR2_EL3
(op0 = 0b11, op1 = 0b110, CRn = 0b0001, CRm = 0b0010, op2 = 0b010)
if !(IsFeatureImplemented(FEAT_SCR2) && HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then X{64}(t) = SCR2_EL3(); end;
MSR SCR2_EL3, <Xt>
(op0 = 0b11, op1 = 0b110, CRn = 0b0001, CRm = 0b0010, op2 = 0b010)
if !(IsFeatureImplemented(FEAT_SCR2) && HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then SCR2_EL3() = X{64}(t); end;
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