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HCRXMASK_EL2

Extended Hypervisor Configuration Masking Register

Mask register to prevent updates of fields in HCRX_EL2 on direct writes to HCRX_EL2.

Configuration

This register is present only when FEAT_SRMASK2 is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to HCRXMASK_EL2 are UNDEFINED.

Attributes

HCRXMASK_EL2 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0FNBVTLBIDOSEnNVnTTLBOSNVnTTLBISNVnTTLB
FDITRES0NVTGESRMASKEnVTLBIDEnPACMEnEnFPMGCSEnEnIDCP128EnSDERRTMEAEnSNERRD128EnPTTWISCTLR2EnTCR2EnRES0MSCEnMCE2CMOWVFNMIVINMITALLINTSMPMEFGTnXSFnXSEnASREnALSEnAS0

Bits [63:37]:

Reserved, RES0.

FNB, bit [36] when FEAT_TLBID is implemented:

Mask bit for FNB.

FNBMeaning
0b0

HCRX_EL2.FNB is writable.

0b1

HCRX_EL2.FNB is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

VTLBIDOSEn, bit [35] when FEAT_TLBID is implemented:

Mask bit for VTLBIDOSEn.

VTLBIDOSEnMeaning
0b0

HCRX_EL2.VTLBIDOSEn is writable.

0b1

HCRX_EL2.VTLBIDOSEn is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

NVnTTLBOS, bit [34] when FEAT_NV3 is implemented:

Mask bit for NVnTTLBOS.

NVnTTLBOSMeaning
0b0

HCRX_EL2.NVnTTLBOS is writable.

0b1

HCRX_EL2.NVnTTLBOS is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

NVnTTLBIS, bit [33] when FEAT_NV3 is implemented:

Mask bit for NVnTTLBIS.

NVnTTLBISMeaning
0b0

HCRX_EL2.NVnTTLBIS is writable.

0b1

HCRX_EL2.NVnTTLBIS is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

NVnTTLB, bit [32] when FEAT_NV3 is implemented:

Mask bit for NVnTTLB.

NVnTTLBMeaning
0b0

HCRX_EL2.NVnTTLB is writable.

0b1

HCRX_EL2.NVnTTLB is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

FDIT, bit [31] when FEAT_FDIT is implemented:

Mask bit for FDIT.

FDITMeaning
0b0

HCRX_EL2.FDIT is writable.

0b1

HCRX_EL2.FDIT is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Bits [30:28]:

Reserved, RES0.

NVTGE, bit [27] when FEAT_NV3 is implemented:

Mask bit for NVTGE.

NVTGEMeaning
0b0

HCRX_EL2.NVTGE is writable.

0b1

HCRX_EL2.NVTGE is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

SRMASKEn, bit [26] when FEAT_SRMASK is implemented:

Mask bit for SRMASKEn.

SRMASKEnMeaning
0b0

HCRX_EL2.SRMASKEn is writable.

0b1

HCRX_EL2.SRMASKEn is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

VTLBIDEn, bit [25] when FEAT_TLBID is implemented:

Mask bit for VTLBIDEn.

VTLBIDEnMeaning
0b0

HCRX_EL2.VTLBIDEn is writable.

0b1

HCRX_EL2.VTLBIDEn is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

PACMEn, bit [24] when FEAT_PAuth_LR is implemented:

Mask bit for PACMEn.

PACMEnMeaning
0b0

HCRX_EL2.PACMEn is writable.

0b1

HCRX_EL2.PACMEn is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

EnFPM, bit [23] when FEAT_FPMR is implemented:

Mask bit for EnFPM.

EnFPMMeaning
0b0

HCRX_EL2.EnFPM is writable.

0b1

HCRX_EL2.EnFPM is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

GCSEn, bit [22] when FEAT_GCS is implemented:

Mask bit for GCSEn.

GCSEnMeaning
0b0

HCRX_EL2.GCSEn is writable.

0b1

HCRX_EL2.GCSEn is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

EnIDCP128, bit [21] when FEAT_SYSREG128 is implemented:

Mask bit for EnIDCP128.

EnIDCP128Meaning
0b0

HCRX_EL2.EnIDCP128 is writable.

0b1

HCRX_EL2.EnIDCP128 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

EnSDERR, bit [20] when FEAT_ADERR is implemented:

Mask bit for EnSDERR.

EnSDERRMeaning
0b0

HCRX_EL2.EnSDERR is writable.

0b1

HCRX_EL2.EnSDERR is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TMEA, bit [19] when FEAT_DoubleFault2 is implemented:

Mask bit for TMEA.

TMEAMeaning
0b0

HCRX_EL2.TMEA is writable.

0b1

HCRX_EL2.TMEA is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

EnSNERR, bit [18] when FEAT_ANERR is implemented:

Mask bit for EnSNERR.

EnSNERRMeaning
0b0

HCRX_EL2.EnSNERR is writable.

0b1

HCRX_EL2.EnSNERR is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

D128En, bit [17] when FEAT_D128 is implemented:

Mask bit for D128En.

D128EnMeaning
0b0

HCRX_EL2.D128En is writable.

0b1

HCRX_EL2.D128En is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

PTTWI, bit [16] when FEAT_THE is implemented:

Mask bit for PTTWI.

PTTWIMeaning
0b0

HCRX_EL2.PTTWI is writable.

0b1

HCRX_EL2.PTTWI is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

SCTLR2En, bit [15] when FEAT_SCTLR2 is implemented:

Mask bit for SCTLR2En.

SCTLR2EnMeaning
0b0

HCRX_EL2.SCTLR2En is writable.

0b1

HCRX_EL2.SCTLR2En is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TCR2En, bit [14] when FEAT_TCR2 is implemented:

Mask bit for TCR2En.

TCR2EnMeaning
0b0

HCRX_EL2.TCR2En is writable.

0b1

HCRX_EL2.TCR2En is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Bits [13:12]:

Reserved, RES0.

MSCEn, bit [11] when FEAT_MOPS is implemented:

Mask bit for MSCEn.

MSCEnMeaning
0b0

HCRX_EL2.MSCEn is writable.

0b1

HCRX_EL2.MSCEn is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

MCE2, bit [10] when FEAT_MOPS is implemented:

Mask bit for MCE2.

MCE2Meaning
0b0

HCRX_EL2.MCE2 is writable.

0b1

HCRX_EL2.MCE2 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

CMOW, bit [9] when FEAT_CMOW is implemented:

Mask bit for CMOW.

CMOWMeaning
0b0

HCRX_EL2.CMOW is writable.

0b1

HCRX_EL2.CMOW is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

VFNMI, bit [8] when FEAT_NMI is implemented:

Mask bit for VFNMI.

VFNMIMeaning
0b0

HCRX_EL2.VFNMI is writable.

0b1

HCRX_EL2.VFNMI is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

VINMI, bit [7] when FEAT_NMI is implemented:

Mask bit for VINMI.

VINMIMeaning
0b0

HCRX_EL2.VINMI is writable.

0b1

HCRX_EL2.VINMI is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TALLINT, bit [6] when FEAT_NMI is implemented:

Mask bit for TALLINT.

TALLINTMeaning
0b0

HCRX_EL2.TALLINT is writable.

0b1

HCRX_EL2.TALLINT is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

SMPME, bit [5] when FEAT_SME is implemented:

Mask bit for SMPME.

SMPMEMeaning
0b0

HCRX_EL2.SMPME is writable.

0b1

HCRX_EL2.SMPME is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

FGTnXS, bit [4] when FEAT_XS is implemented:

Mask bit for FGTnXS.

FGTnXSMeaning
0b0

HCRX_EL2.FGTnXS is writable.

0b1

HCRX_EL2.FGTnXS is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

FnXS, bit [3] when FEAT_XS is implemented:

Mask bit for FnXS.

FnXSMeaning
0b0

HCRX_EL2.FnXS is writable.

0b1

HCRX_EL2.FnXS is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

EnASR, bit [2] when FEAT_LS64_V is implemented:

Mask bit for EnASR.

EnASRMeaning
0b0

HCRX_EL2.EnASR is writable.

0b1

HCRX_EL2.EnASR is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

EnALS, bit [1] when FEAT_LS64 is implemented:

Mask bit for EnALS.

EnALSMeaning
0b0

HCRX_EL2.EnALS is writable.

0b1

HCRX_EL2.EnALS is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

EnAS0, bit [0] when FEAT_LS64_ACCDATA is implemented:

Mask bit for EnAS0.

EnAS0Meaning
0b0

HCRX_EL2.EnAS0 is writable.

0b1

HCRX_EL2.EnAS0 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, HCRXMASK_EL2

(op0 = 0b11, op1 = 0b100, CRn = 0b0001, CRm = 0b0101, op2 = 0b111)

if !(IsFeatureImplemented(FEAT_SRMASK2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR2_EL3().SRMASK2En == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCRX_EL2_NVTGE() == '1' && (!HaveEL(EL3) || SCR2_EL3().SRMASK2En == '1') then X{64}(t) = NVHCRXMASK_EL2(); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_SCR2) && SCR2_EL3().SRMASK2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = HCRXMASK_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = HCRXMASK_EL2(); end;

MSR HCRXMASK_EL2, <Xt>

(op0 = 0b11, op1 = 0b100, CRn = 0b0001, CRm = 0b0101, op2 = 0b111)

if !(IsFeatureImplemented(FEAT_SRMASK2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR2_EL3().SRMASK2En == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCRX_EL2_NVTGE() == '1' && (!HaveEL(EL3) || SCR2_EL3().SRMASK2En == '1') then if !IsZero(NVHCRXMASK_EL2()) then Undefined(); else NVHCRXMASK_EL2() = X{64}(t); end; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_SCR2) && SCR2_EL3().SRMASK2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif !IsZero(HCRXMASK_EL2()) then Undefined(); else HCRXMASK_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then HCRXMASK_EL2() = X{64}(t); end;

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