NVHCRXMASK_EL2

This register is present only when FEAT_NV3 is implemented, FEAT_SRMASK2 is implemented, and FEAT_AA64 is implemented. Otherwise, direct accesses to NVHCRXMASK_EL2 are UNDEFINED.

FNB	Meaning
0b0	NVHCRX_EL2.FNB is writable.
0b1	NVHCRX_EL2.FNB is not writable.

VTLBIDOSEn	Meaning
0b0	NVHCRX_EL2.VTLBIDOSEn is writable.
0b1	NVHCRX_EL2.VTLBIDOSEn is not writable.

NVnTTLBOS	Meaning
0b0	NVHCRX_EL2.NVnTTLBOS is writable.
0b1	NVHCRX_EL2.NVnTTLBOS is not writable.

NVnTTLBIS	Meaning
0b0	NVHCRX_EL2.NVnTTLBIS is writable.
0b1	NVHCRX_EL2.NVnTTLBIS is not writable.

NVnTTLB	Meaning
0b0	NVHCRX_EL2.NVnTTLB is writable.
0b1	NVHCRX_EL2.NVnTTLB is not writable.

FDIT	Meaning
0b0	NVHCRX_EL2.FDIT is writable.
0b1	NVHCRX_EL2.FDIT is not writable.

NVTGE	Meaning
0b0	NVHCRX_EL2.NVTGE is writable.
0b1	NVHCRX_EL2.NVTGE is not writable.

SRMASKEn	Meaning
0b0	NVHCRX_EL2.SRMASKEn is writable.
0b1	NVHCRX_EL2.SRMASKEn is not writable.

VTLBIDEn	Meaning
0b0	NVHCRX_EL2.VTLBIDEn is writable.
0b1	NVHCRX_EL2.VTLBIDEn is not writable.

PACMEn	Meaning
0b0	NVHCRX_EL2.PACMEn is writable.
0b1	NVHCRX_EL2.PACMEn is not writable.

EnFPM	Meaning
0b0	NVHCRX_EL2.EnFPM is writable.
0b1	NVHCRX_EL2.EnFPM is not writable.

GCSEn	Meaning
0b0	NVHCRX_EL2.GCSEn is writable.
0b1	NVHCRX_EL2.GCSEn is not writable.

EnIDCP128	Meaning
0b0	NVHCRX_EL2.EnIDCP128 is writable.
0b1	NVHCRX_EL2.EnIDCP128 is not writable.

EnSDERR	Meaning
0b0	NVHCRX_EL2.EnSDERR is writable.
0b1	NVHCRX_EL2.EnSDERR is not writable.

TMEA	Meaning
0b0	NVHCRX_EL2.TMEA is writable.
0b1	NVHCRX_EL2.TMEA is not writable.

EnSNERR	Meaning
0b0	NVHCRX_EL2.EnSNERR is writable.
0b1	NVHCRX_EL2.EnSNERR is not writable.

D128En	Meaning
0b0	NVHCRX_EL2.D128En is writable.
0b1	NVHCRX_EL2.D128En is not writable.

PTTWI	Meaning
0b0	NVHCRX_EL2.PTTWI is writable.
0b1	NVHCRX_EL2.PTTWI is not writable.

SCTLR2En	Meaning
0b0	NVHCRX_EL2.SCTLR2En is writable.
0b1	NVHCRX_EL2.SCTLR2En is not writable.

TCR2En	Meaning
0b0	NVHCRX_EL2.TCR2En is writable.
0b1	NVHCRX_EL2.TCR2En is not writable.

MSCEn	Meaning
0b0	NVHCRX_EL2.MSCEn is writable.
0b1	NVHCRX_EL2.MSCEn is not writable.

MCE2	Meaning
0b0	NVHCRX_EL2.MCE2 is writable.
0b1	NVHCRX_EL2.MCE2 is not writable.

CMOW	Meaning
0b0	NVHCRX_EL2.CMOW is writable.
0b1	NVHCRX_EL2.CMOW is not writable.

VFNMI	Meaning
0b0	NVHCRX_EL2.VFNMI is writable.
0b1	NVHCRX_EL2.VFNMI is not writable.

VINMI	Meaning
0b0	NVHCRX_EL2.VINMI is writable.
0b1	NVHCRX_EL2.VINMI is not writable.

TALLINT	Meaning
0b0	NVHCRX_EL2.TALLINT is writable.
0b1	NVHCRX_EL2.TALLINT is not writable.

SMPME	Meaning
0b0	NVHCRX_EL2.SMPME is writable.
0b1	NVHCRX_EL2.SMPME is not writable.

FGTnXS	Meaning
0b0	NVHCRX_EL2.FGTnXS is writable.
0b1	NVHCRX_EL2.FGTnXS is not writable.

FnXS	Meaning
0b0	NVHCRX_EL2.FnXS is writable.
0b1	NVHCRX_EL2.FnXS is not writable.

EnASR	Meaning
0b0	NVHCRX_EL2.EnASR is writable.
0b1	NVHCRX_EL2.EnASR is not writable.

EnALS	Meaning
0b0	NVHCRX_EL2.EnALS is writable.
0b1	NVHCRX_EL2.EnALS is not writable.

EnAS0	Meaning
0b0	NVHCRX_EL2.EnAS0 is writable.
0b1	NVHCRX_EL2.EnAS0 is not writable.

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, NVHCRXMASK_EL2

(op0 = 0b11, op1 = 0b100, CRn = 0b0001, CRm = 0b0101, op2 = 0b101)

if !(IsFeatureImplemented(FEAT_NV3) && IsFeatureImplemented(FEAT_SRMASK2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR2_EL3().SRMASK2En == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if IsFeatureImplemented(FEAT_NV3) && EffectiveHCRX_EL2_NVTGE() == '1' then X{64}(t) = NVMem(0x0F8); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_SCR2) && SCR2_EL3().SRMASK2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = NVHCRXMASK_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = NVHCRXMASK_EL2(); end;

MSR NVHCRXMASK_EL2, <Xt>

(op0 = 0b11, op1 = 0b100, CRn = 0b0001, CRm = 0b0101, op2 = 0b101)

if !(IsFeatureImplemented(FEAT_NV3) && IsFeatureImplemented(FEAT_SRMASK2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR2_EL3().SRMASK2En == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if IsFeatureImplemented(FEAT_NV3) && EffectiveHCRX_EL2_NVTGE() == '1' then NVMem(0x0F8) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_SCR2) && SCR2_EL3().SRMASK2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else NVHCRXMASK_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then NVHCRXMASK_EL2() = X{64}(t); end;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																											FNB	VTLBIDOSEn	NVnTTLBOS	NVnTTLBIS	NVnTTLB
FDIT	RES0			NVTGE	SRMASKEn	VTLBIDEn	PACMEn	EnFPM	GCSEn	EnIDCP128	EnSDERR	TMEA	EnSNERR	D128En	PTTWI	SCTLR2En	TCR2En	RES0		MSCEn	MCE2	CMOW	VFNMI	VINMI	TALLINT	SMPME	FGTnXS	FnXS	EnASR	EnALS	EnAS0

Configuration

Attributes

Field descriptions

Bits [63:37]:

FNB, bit [36] when FEAT_TLBID is implemented:

Otherwise:

VTLBIDOSEn, bit [35] when FEAT_TLBID is implemented:

Otherwise:

NVnTTLBOS, bit [34] when FEAT_NV3 is implemented:

Otherwise:

NVnTTLBIS, bit [33] when FEAT_NV3 is implemented:

Otherwise:

NVnTTLB, bit [32] when FEAT_NV3 is implemented:

Otherwise:

FDIT, bit [31] when FEAT_FDIT is implemented:

Otherwise:

Bits [30:28]:

NVTGE, bit [27] when FEAT_NV3 is implemented:

Otherwise:

SRMASKEn, bit [26] when FEAT_SRMASK is implemented:

Otherwise:

VTLBIDEn, bit [25] when FEAT_TLBID is implemented:

Otherwise:

PACMEn, bit [24] when FEAT_PAuth_LR is implemented:

Otherwise:

EnFPM, bit [23] when FEAT_FPMR is implemented:

Otherwise:

GCSEn, bit [22] when FEAT_GCS is implemented:

Otherwise:

EnIDCP128, bit [21] when FEAT_SYSREG128 is implemented:

Otherwise:

EnSDERR, bit [20] when FEAT_ADERR is implemented:

Otherwise:

TMEA, bit [19] when FEAT_DoubleFault2 is implemented:

Otherwise:

EnSNERR, bit [18] when FEAT_ANERR is implemented:

Otherwise:

D128En, bit [17] when FEAT_D128 is implemented:

Otherwise:

PTTWI, bit [16] when FEAT_THE is implemented:

Otherwise:

SCTLR2En, bit [15] when FEAT_SCTLR2 is implemented:

Otherwise:

TCR2En, bit [14] when FEAT_TCR2 is implemented:

Otherwise:

Bits [13:12]:

MSCEn, bit [11] when FEAT_MOPS is implemented:

Otherwise:

MCE2, bit [10] when FEAT_MOPS is implemented:

Otherwise:

CMOW, bit [9] when FEAT_CMOW is implemented:

Otherwise:

VFNMI, bit [8] when FEAT_NMI is implemented:

Otherwise:

VINMI, bit [7] when FEAT_NMI is implemented:

Otherwise:

TALLINT, bit [6] when FEAT_NMI is implemented:

Otherwise:

SMPME, bit [5] when FEAT_SME is implemented:

Otherwise:

FGTnXS, bit [4] when FEAT_XS is implemented:

Otherwise:

FnXS, bit [3] when FEAT_XS is implemented:

Otherwise:

EnASR, bit [2] when FEAT_LS64_V is implemented:

Otherwise:

EnALS, bit [1] when FEAT_LS64 is implemented:

Otherwise:

EnAS0, bit [0] when FEAT_LS64_ACCDATA is implemented:

Otherwise:

Access Instructions