MPAM2 Register (EL2)
Holds information to generate MPAM labels for memory requests when executing at EL2.
AArch64 System register MPAM2_EL2 bit [63] is architecturally mapped to AArch64 System register MPAM3_EL3[63] when (FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p0 is implemented) and EL3 is implemented.
AArch64 System register MPAM2_EL2 bit [63] is architecturally mapped to AArch64 System register MPAM1_EL1[63] when FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p0 is implemented.
This register is present only when FEAT_MPAM is implemented and FEAT_AA64EL2 is implemented. Otherwise, direct accesses to MPAM2_EL2 are UNDEFINED.
This register has no effect on execution at EL1 and EL0, if EL2 is not enabled in the current Security state.
MPAM2_EL2 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| altPMG | PMG | ||||||||||||||||||||||||||||||
| altPARTID | PARTID | ||||||||||||||||||||||||||||||
Alternative performance monitoring group for accesses made from EL2.
The reset behavior of this field is:
Reserved, RES0.
Performance monitoring group for accesses made from EL2.
The reset behavior of this field is:
Alternative Partition ID for accesses made from EL2.
The reset behavior of this field is:
Reserved, RES0.
Partition ID for accesses made from EL2.
The reset behavior of this field is:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MPAMEN | RES0 | TIDR | RES0 | ALTSP_HFC | ALTSP_EL2 | ALTSP_FRCD | RES0 | EnMPAMSM | TRAPMPAM0EL1 | TRAPMPAM1EL1 | PMG_D | PMG_I | |||||||||||||||||||
| PARTID_D | PARTID_I | ||||||||||||||||||||||||||||||
MPAM Enable. MPAM is enabled when MPAMEN == 1. When disabled, all PARTIDs and PMGs are output as their default value in the corresponding ID space.
| MPAMEN | Meaning |
|---|---|
| 0b0 |
The default PARTID and default PMG are output in MPAM information from all Exception levels. |
| 0b1 |
MPAM information is output based on the MPAMn_ELx register for ELn according to the MPAM configuration. |
If EL3 is implemented, this field is read-only and reads the current value of the read/write MPAM3_EL3.MPAMEN bit.
The reset behavior of this field is:
Accessing this field has the following behavior:
Reserved, RES0.
TIDR traps accesses to MPAMIDR_EL1 from EL1 to EL2.
| TIDR | Meaning |
|---|---|
| 0b0 |
This control does not cause any instructions to be trapped. |
| 0b1 |
Trap accesses to MPAMIDR_EL1 from EL1 to EL2. |
MPAMHCR_EL2.TRAP_MPAMIDR_EL1 == 1 also traps MPAMIDR_EL1 accesses from EL1 to EL2. If either TIDR or TRAP_MPAMIDR_EL1 are 1, accesses are trapped.
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Hierarchical force of alternative PARTID space controls. When MPAM3_EL3.ALTSP_HEN is 0, ALTSP controls in MPAM2_EL2 have no effect. When MPAM3_EL3.ALTSP_HEN is 1, this bit selects whether the PARTIDs in MPAM1_EL1 and MPAM0_EL1 are in the primary (0) or alternative (1) PARTID space for the security state.
| ALTSP_HFC | Meaning |
|---|---|
| 0b0 |
When MPAM3_EL3.ALTSP_HEN is 1, the PARTID space of MPAM1_EL1.PARTID_I, MPAM1_EL1.PARTID_D, MPAM0_EL1.PARTID_I, and MPAM0_EL1.PARTID_D are in the primary PARTID space for the Security state. |
| 0b1 |
When MPAM3_EL3.ALTSP_HEN is 1, the PARTID space of MPAM1_EL1.PARTID_I, MPAM1_EL1.PARTID_D, MPAM0_EL1.PARTID_I, and MPAM0_EL1.PARTID_D are in the alternative PARTID space for the Security state. |
This control has no effect when MPAM3_EL3.ALTSP_HEN is 0.
For more information, see 'In a PE with FEAT_RME, selection of primary or alternative PARTID space'.
The reset behavior of this field is:
Reserved, RES0.
Select alternative PARTID space for PARTIDs in MPAM2_EL2 when MPAM3_EL3.ALTSP_HEN is 1.
| ALTSP_EL2 | Meaning |
|---|---|
| 0b0 |
When MPAM3_EL3.ALTSP_HEN is 1, selects the primary PARTID space for MPAM2_EL2.PARTID_I and MPAM2_EL2.PARTID_D. |
| 0b1 |
When MPAM3_EL3.ALTSP_HEN is 1, selects the alternative PARTID space for MPAM2_EL2.PARTID_I and MPAM2_EL2.PARTID_D. |
For more information, see 'In a PE with FEAT_RME, selection of primary or alternative PARTID space'.
The reset behavior of this field is:
Reserved, RES0.
Alternative PARTID forced for PARTIDs in this register.
| ALTSP_FRCD | Meaning |
|---|---|
| 0b0 |
The PARTIDs in this register are using the primary PARTID space. |
| 0b1 |
The PARTIDs in this register are using the alternative PARTID space. |
This bit indicates that a higher Exception level has forced the PARTIDs in this register to use the alternative PARTID space defined for the current Security state. In EL2, it is also 1 when MPAM2_EL2.ALTSP_EL2 is 1.
For more information, see 'In a PE with FEAT_RME, selection of primary or alternative PARTID space'.
The reset behavior of this field is:
Accessing this field has the following behavior:
Reserved, RES0.
Reserved, RES0.
Traps execution at EL1 of instructions that directly access the MPAMSM_EL1 register to EL2. The exception is reported using ESR_ELx.EC syndrome value 0x18.
| EnMPAMSM | Meaning |
|---|---|
| 0b0 |
This control causes execution of these instructions at EL1 to be trapped. |
| 0b1 |
This control does not cause execution of any instructions to be trapped. |
This field has no effect on accesses to MPAMSM_EL1 from EL2 or EL3.
The reset behavior of this field is:
Reserved, RES0.
Trap accesses from EL1 to the MPAM0_EL1 register trap to EL2.
| TRAPMPAM0EL1 | Meaning |
|---|---|
| 0b0 |
Accesses to MPAM0_EL1 from EL1 are not trapped. |
| 0b1 |
Accesses to MPAM0_EL1 from EL1 are trapped to EL2. |
The reset behavior of this field is:
Trap accesses from EL1 to the MPAM1_EL1 register trap to EL2.
| TRAPMPAM1EL1 | Meaning |
|---|---|
| 0b0 |
Accesses to MPAM1_EL1 from EL1 are not trapped. |
| 0b1 |
Accesses to MPAM1_EL1 from EL1 are trapped to EL2. |
The reset behavior of this field is:
Performance monitoring group for data accesses.
The reset behavior of this field is:
Performance monitoring group for instruction accesses.
The reset behavior of this field is:
Partition ID for data accesses, including load and store accesses, made from EL2.
The reset behavior of this field is:
Partition ID for instruction accesses made from EL2.
The reset behavior of this field is:
When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL2 using the accessor name MPAM2_EL2 or MPAM1_EL1 are not guaranteed to be ordered with respect to accesses using the other accessor name.
None of the fields in this register are permitted to be cached in a TLB.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, MPAM2_EL2
(op0 = 0b11, op1 = 0b100, CRn = 0b1010, CRm = 0b0101, op2 = 0b000)
if !(IsFeatureImplemented(FEAT_MPAM) && IsFeatureImplemented(FEAT_AA64EL2)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else AArch64_SystemAccessTrap(EL2, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = MPAM2_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = MPAM2_EL2(); end;
MSR MPAM2_EL2, <Xt>
(op0 = 0b11, op1 = 0b100, CRn = 0b1010, CRm = 0b0101, op2 = 0b000)
if !(IsFeatureImplemented(FEAT_MPAM) && IsFeatureImplemented(FEAT_AA64EL2)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else AArch64_SystemAccessTrap(EL2, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else MPAM2_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then MPAM2_EL2() = X{64}(t); end;
MRS <Xt>, MPAM1_EL1
(op0 = 0b11, op1 = 0b000, CRn = 0b1010, CRm = 0b0101, op2 = 0b000)
if !IsFeatureImplemented(FEAT_MPAM) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EL2Enabled() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM2_EL2().TRAPMPAM1EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_MPAMv2) && MPAMHCR_EL2().nTRAPMPAM1EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x900); else X{64}(t) = MPAM1_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = MPAM2_EL2(); else X{64}(t) = MPAM1_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = MPAM1_EL1(); end;
MSR MPAM1_EL1, <Xt>
(op0 = 0b11, op1 = 0b000, CRn = 0b1010, CRm = 0b0101, op2 = 0b000)
if !IsFeatureImplemented(FEAT_MPAM) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EL2Enabled() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM2_EL2().TRAPMPAM1EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_MPAMv2) && MPAMHCR_EL2().nTRAPMPAM1EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x900) = X{64}(t); else MPAM1_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then MPAM2_EL2() = X{64}(t); else MPAM1_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then MPAM1_EL1() = X{64}(t); end;
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