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MPAMIDR_EL1

MPAM ID Register (EL1)

Indicates the maximum PARTID and PMG values supported in the implementation and the support for other optional features.

Configuration

This register is present only when FEAT_MPAM is implemented. Otherwise, direct accesses to MPAMIDR_EL1 are UNDEFINED.

Attributes

MPAMIDR_EL1 is a 64-bit register.

Field descriptions

When FEAT_MPAMv2 is implemented:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0HAS_BW_CTRLRES0PMG_MAX
RES0HAS_INSTR_ALT_IDHAS_ALT_IDRES0HAS_HCRRES0PARTID_MAX

Bits [63:57]:

Reserved, RES0.

HAS_BW_CTRL, bit [56]:

Indicates support for PE-side bandwidth controls.

The value of this field is an IMPLEMENTATION DEFINED choice of:

HAS_BW_CTRLMeaning
0b0

Support for PE-side bandwidth controls is not implemented.

0b1

Support for PE-side bandwidth controls is implemented using MPAMBW registers.

FEAT_MPAM_PE_BW_CTRL implements the functionality identified by the value 1.

Access to this field is RO.

Bits [55:48]:

Reserved, RES0.

PMG_MAX, bits [47:32]:

Indicates the largest value of PMG supported by the implementation. The PMG field of every MPAMn_ELx register must implement at least enough bits to represent this value.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Bits [31:23]:

Reserved, RES0.

HAS_INSTR_ALT_ID, bit [22] when MPAMIDR_EL1.HAS_ALT_ID == '1':

Indicates support for tagging instruction fetches generated by PE traffic with the configured alternative PARTID and PMG values.

The value of this field is an IMPLEMENTATION DEFINED choice of:

HAS_INSTR_ALT_IDMeaning
0b0

Support for tagging instruction fetches with alternative PARTID and PMG values is not implemented.

0b1

Support for tagging instruction fetches with alternative PARTID and PMG values is implemented.

Access to this field is RO.

Otherwise:

Reserved, RES0.

HAS_ALT_ID, bit [21]:

Indicates support for configuring and using alternative PARTID and PMG values.

The value of this field is an IMPLEMENTATION DEFINED choice of:

HAS_ALT_IDMeaning
0b0

Support for alternative PARTID and PMG values is not implemented.

0b1

Support for alternative PARTID and PMG values is implemented.

Access to this field is RO.

Bits [20:18]:

Reserved, RES0.

HAS_HCR, bit [17]:

Indicates support for MPAM virtualization.

The value of this field is an IMPLEMENTATION DEFINED choice of:

HAS_HCRMeaning
0b0

Support for MPAM virtualization is not implemented.

0b1

Support for MPAM virtualization is implemented.

HAS_HCR indicates that the PE implementation supports MPAM virtualization. Must be 0 if EL2 is not implemented in either Security state.

When FEAT_MPAMv2 is implemented, this field does not indicate whether MPAMHCR_EL2 is implemented. Also, the registers MPAMVPMV_EL2, and MPAMVPM<n>_EL2 used for legacy MPAM virtualization are not implemented.

Access to this field is RO.

Bit [16]:

Reserved, RES0.

PARTID_MAX, bits [15:0]:

Indicates the largest value of PARTID supported by the implementation. The PARTID field of every MPAMn_ELx register must implement at least enough bits to represent this value.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Otherwise:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0HAS_SDEFLTHAS_FORCE_NSSP4HAS_TIDRHAS_ALTSPHAS_BW_CTRLRES0PMG_MAX
RES0VPMR_MAXHAS_HCRRES0PARTID_MAX

Bits [63:62]:

Reserved, RES0.

HAS_SDEFLT, bit [61]:

HAS_SDEFLT indicates support for MPAM3_EL3.SDEFLT bit.

The value of this field is an IMPLEMENTATION DEFINED choice of:

HAS_SDEFLTMeaning
0b0

The SDEFLT bit is not implemented in MPAM3_EL3.

0b1

The SDEFLT bit is implemented in MPAM3_EL3.

When MPAM3_EL3.SDEFLT == 1, accesses from the Secure Execution state use the default PARTID, PARTID == 0.

Access to this field is RO.

HAS_FORCE_NS, bit [60]:

HAS_FORCE_NS indicates support for MPAM3_EL3.FORCE_NS bit.

The value of this field is an IMPLEMENTATION DEFINED choice of:

HAS_FORCE_NSMeaning
0b0

The FORCE_NS bit is not implemented in MPAM3_EL3.

0b1

The FORCE_NS bit is implemented in MPAM3_EL3.

When MPAM3_EL3.FORCE_NS == 1, accesses from the Secure Execution state have MPAM_NS == 1.

Access to this field is RO.

SP4, bit [59]:

Supports 4 MPAM PARTID spaces.

The value of this field is an IMPLEMENTATION DEFINED choice of:

SP4Meaning
0b0

MPAM supports 2 PARTID spaces.

0b1

MPAM supports 4 PARTID spaces.

Access to this field is RO.

HAS_TIDR, bit [58]:

HAS_TIDR indicates support for MPAM2_EL2.TIDR bit.

The value of this field is an IMPLEMENTATION DEFINED choice of:

HAS_TIDRMeaning
0b0

The TIDR bit is not implemented in MPAM2_EL2.

0b1

The TIDR bit is implemented in MPAM2_EL2.

Arm recommends that when the MPAM version is MPAM v0.1 or MPAM v1.1, MPAMIDR_EL1.HAS_TIDR is 1 and that the MPAM2_EL2.TIDR field is implemented.

Access to this field is RO.

HAS_ALTSP, bit [57]:

HAS_ALTSP indicates support for alternative PARTID spaces.

The value of this field is an IMPLEMENTATION DEFINED choice of:

HAS_ALTSPMeaning
0b0

Alternative PARTID spaces are not implemented.

0b1

Alternative PARTID spaces are implemented with control bits in MPAM3_EL3 and MPAM2_EL2.

Access to this field is RO.

HAS_BW_CTRL, bit [56]:

HAS_BW_CTRL indicates support for PE-side bandwidth controls.

The value of this field is an IMPLEMENTATION DEFINED choice of:

HAS_BW_CTRLMeaning
0b0

PE-side bandwidth controls are not implemented.

0b1

PE-side bandwidth controls are implemented.

FEAT_MPAM_PE_BW_CTRL implements the functionality identified by the value 1.

Access to this field is RO.

Bits [55:40]:

Reserved, RES0.

PMG_MAX, bits [39:32]:

The largest value of PMG that the implementation can generate. The PMG_I and PMG_D fields of every MPAMn_ELx must implement at least enough bits to represent PMG_MAX.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Bits [31:21]:

Reserved, RES0.

VPMR_MAX, bits [20:18] when MPAMIDR_EL1.HAS_HCR == '1':

Indicates the maximum register index n for the MPAMVPM<n>_EL2 registers.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Otherwise:

Reserved, RAZ.

HAS_HCR, bit [17]:

HAS_HCR indicates that the PE implementation supports MPAM virtualization, including MPAMHCR_EL2, MPAMVPMV_EL2, and MPAMVPM<n>_EL2 with n in the range 0 to VPMR_MAX. Must be 0 if EL2 is not implemented in either Security state.

The value of this field is an IMPLEMENTATION DEFINED choice of:

HAS_HCRMeaning
0b0

MPAM virtualization is not supported.

0b1

MPAM virtualization is supported.

Access to this field is RO.

Bit [16]:

Reserved, RES0.

PARTID_MAX, bits [15:0]:

The largest value of PARTID that the implementation can generate. The PARTID_I and PARTID_D fields of every MPAMn_ELx must implement at least enough bits to represent PARTID_MAX.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, MPAMIDR_EL1

(op0 = 0b11, op1 = 0b000, CRn = 0b1010, CRm = 0b0100, op2 = 0b100)

if !IsFeatureImplemented(FEAT_MPAM) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EL2Enabled() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAMIDR_EL1().HAS_HCR == '1' && MPAMHCR_EL2().TRAP_MPAMIDR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAMIDR_EL1().HAS_TIDR == '1' && MPAM2_EL2().TIDR == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_MPAMv2) && MPAMHCR_EL2().nTIDR == '0' then AArch64_SystemAccessTrap(EL2, 0x18); else X{64}(t) = MPAMIDR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = MPAMIDR_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = MPAMIDR_EL1(); end;

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