MPAM1 Register (EL1)
Holds information to generate MPAM labels for memory requests when executing at EL1.
AArch64 System register MPAM1_EL1 bit [63] is architecturally mapped to AArch64 System register MPAM3_EL3[63] when (FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p0 is implemented) and EL3 is implemented.
AArch64 System register MPAM1_EL1 bit [63] is architecturally mapped to AArch64 System register MPAM2_EL2[63] when (FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p0 is implemented), EL3 is not implemented, and EL2 is implemented.
This register is present only when FEAT_MPAM is implemented. Otherwise, direct accesses to MPAM1_EL1 are UNDEFINED.
If FEAT_MPAMv1p0 or FEAT_MPAMv0p1 is implemented, EL2 is implemented and enabled in the current Security state, and the MPAM virtualization option is present, then:
If MPAMHCR_EL2.GSTAPP_PLK == 1 and the Effective value of HCR_EL2.TGE is 0, MPAM1_EL1 is used instead of MPAM0_EL1 to generate MPAM labels for memory requests when executing at EL0.
If MPAMHCR_EL2.EL1_VPMEN == 1, MPAM PARTIDs in MPAM1_EL1 are virtual and mapped into physical PARTIDs for the current Security state. This mapping of MPAM1_EL1 virtual PARTIDs to physical PARTIDs when EL1_VPMEN is 1 also applies when MPAM1_EL1 is used at EL0 due to MPAMHCR_EL2.GSTAPP_PLK.
MPAM1_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| altPMG | PMG | ||||||||||||||||||||||||||||||
| altPARTID | PARTID | ||||||||||||||||||||||||||||||
Alternative performance monitoring group for accesses made from EL1.
The reset behavior of this field is:
Reserved, RES0.
Performance monitoring group for accesses made from EL1.
The reset behavior of this field is:
Alternative Partition ID for accesses made from EL1.
The reset behavior of this field is:
Reserved, RES0.
Partition ID for accesses made from EL1.
The reset behavior of this field is:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MPAMEN | RES0 | FORCED_NS | RES0 | ALTSP_FRCD | RES0 | PMG_D | PMG_I | ||||||||||||||||||||||||
| PARTID_D | PARTID_I | ||||||||||||||||||||||||||||||
MPAM Enable. MPAM is enabled when MPAMEN == 1. When disabled, all PARTIDs and PMGs are output as their default value in the corresponding ID space.
| MPAMEN | Meaning |
|---|---|
| 0b0 |
The default PARTID and default PMG are output in MPAM information. |
| 0b1 |
MPAM information is output based on the MPAMn_ELx register for ELn according the MPAM configuration. |
The reset behavior of this field is:
Accessing this field has the following behavior:
Reserved, RES0.
In the Secure state, FORCED_NS indicates the state of MPAM3_EL3.FORCE_NS.
| FORCED_NS | Meaning |
|---|---|
| 0b0 | In the Non-secure state, always reads as 0. In the Secure state, indicates that MPAM3_EL3.FORCE_NS == 0. |
| 0b1 |
In the Secure state, indicates that MPAM3_EL3.FORCE_NS == 1. |
Always reads as 0 in the Non-secure state.
Writes are ignored.
Access to this field is RO.
Reserved, RES0.
Reserved, RES0.
Alternative PARTID forced for PARTIDs in this register.
| ALTSP_FRCD | Meaning |
|---|---|
| 0b0 |
The PARTIDs in MPAM1_EL1 and MPAM0_EL1 are using the primary PARTID space. |
| 0b1 |
The PARTIDs in MPAM1_EL1 and MPAM0_EL1 are using the alternative PARTID space. |
This bit indicates that a higher Exception level has forced the PARTIDs in this register to use the alternative PARTID space defined for the current Security state.
In MPAM1_EL1, it also indicates that MPAM0_EL1 is forced to use alternative PARTID space.
For more information, see 'In a PE with FEAT_RME, selection of primary or alternative PARTID space'.
Accessing this field has the following behavior:
Reserved, RES0.
Reserved, RES0.
Performance monitoring group property for PARTID_D.
The reset behavior of this field is:
Performance monitoring group property for PARTID_I.
The reset behavior of this field is:
Partition ID for data accesses, including load and store accesses, made from EL1.
The reset behavior of this field is:
Partition ID for instruction accesses made from EL1.
The reset behavior of this field is:
When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name MPAM1_EL1 or MPAM1_EL12 are not guaranteed to be ordered with respect to accesses using the other accessor name.
None of the fields in this register are permitted to be cached in a TLB.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, MPAM1_EL1
(op0 = 0b11, op1 = 0b000, CRn = 0b1010, CRm = 0b0101, op2 = 0b000)
if !IsFeatureImplemented(FEAT_MPAM) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EL2Enabled() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM2_EL2().TRAPMPAM1EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_MPAMv2) && MPAMHCR_EL2().nTRAPMPAM1EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x900); else X{64}(t) = MPAM1_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = MPAM2_EL2(); else X{64}(t) = MPAM1_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = MPAM1_EL1(); end;
MSR MPAM1_EL1, <Xt>
(op0 = 0b11, op1 = 0b000, CRn = 0b1010, CRm = 0b0101, op2 = 0b000)
if !IsFeatureImplemented(FEAT_MPAM) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EL2Enabled() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM2_EL2().TRAPMPAM1EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_MPAMv2) && MPAMHCR_EL2().nTRAPMPAM1EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x900) = X{64}(t); else MPAM1_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then MPAM2_EL2() = X{64}(t); else MPAM1_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then MPAM1_EL1() = X{64}(t); end;
MRS <Xt>, MPAM1_EL12
(op0 = 0b11, op1 = 0b101, CRn = 0b1010, CRm = 0b0101, op2 = 0b000)
if !IsFeatureImplemented(FEAT_MPAM) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then X{64}(t) = NVMem(0x900); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else AArch64_SystemAccessTrap(EL2, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = MPAM1_EL1(); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X{64}(t) = MPAM1_EL1(); else Undefined(); end; end;
MSR MPAM1_EL12, <Xt>
(op0 = 0b11, op1 = 0b101, CRn = 0b1010, CRm = 0b0101, op2 = 0b000)
if !IsFeatureImplemented(FEAT_MPAM) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem(0x900) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else AArch64_SystemAccessTrap(EL2, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else MPAM1_EL1() = X{64}(t); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then MPAM1_EL1() = X{64}(t); else Undefined(); end; end;
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