MPAM Control Register (EL1)
Controls the generation of MPAM information for memory requests when executing at EL1 and EL0.
AArch64 System register MPAMCTL_EL1 bit [63] is architecturally mapped to AArch64 System register MPAMCTL_EL3[63] when EL3 is implemented.
AArch64 System register MPAMCTL_EL1 bit [63] is architecturally mapped to AArch64 System register MPAMCTL_EL2[63] when EL3 is not implemented and EL2 is implemented.
This register is present only when FEAT_MPAMv2 is implemented. Otherwise, direct accesses to MPAMCTL_EL1 are UNDEFINED.
MPAMCTL_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MPAMEN | RES0 | EN_ALT_IPMG | EN_ALT_IPARTID | EN_ALT_IPMG_EL0 | EN_ALT_IPARTID_EL0 | RES0 | |||||||||||||||||||||||||
| RES0 | |||||||||||||||||||||||||||||||
MPAM Enable. MPAM is enabled when MPAMEN == 1. When disabled, all PARTIDs and PMGs are output as their default value in the corresponding ID space.
| MPAMEN | Meaning |
|---|---|
| 0b0 |
The default PARTID and default PMG are output in MPAM information from all Exception levels. |
| 0b1 |
MPAM information is output based on the MPAMn_ELx register for ELn according to the MPAM configuration. |
The reset behavior of this field is:
Accessing this field has the following behavior:
Reserved, RES0.
Enables use of the alternative PMG configured in MPAM1_EL1.altPMG for instruction fetch accesses originating at EL1.
| EN_ALT_IPMG | Meaning |
|---|---|
| 0b0 |
The alternative PMG configured in MPAM1_EL1.altPMG is not used for generating MPAM information for instruction fetch accesses. |
| 0b1 |
The alternative PMG configured in MPAM1_EL1.altPMG is used for generating MPAM information for instruction fetch accesses. |
The reset behavior of this field is:
Reserved, RES0.
Enables use of the alternative PARTID configured in MPAM1_EL1.altPARTID for instruction fetch accesses originating at EL1.
| EN_ALT_IPARTID | Meaning |
|---|---|
| 0b0 |
The alternative PARTID configured in MPAM1_EL1.altPARTID is not used for generating MPAM information for instruction fetch accesses. |
| 0b1 |
The alternative PARTID configured in MPAM1_EL1.altPARTID is used for generating MPAM information for instruction fetch accesses. |
The reset behavior of this field is:
Reserved, RES0.
Enables use of the alternative PMG configured in MPAM0_EL1.altPMG for instruction fetch accesses originating at EL0.
| EN_ALT_IPMG_EL0 | Meaning |
|---|---|
| 0b0 |
The alternative PMG configured in MPAM0_EL1.altPMG is not used for generating MPAM information for instruction fetch accesses. |
| 0b1 |
The alternative PMG configured in MPAM0_EL1.altPMG is used for generating MPAM information for instruction fetch accesses. |
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on execution at EL0.
The reset behavior of this field is:
Reserved, RES0.
Enables use of the alternative PARTID configured in MPAM0_EL1.altPARTID for instruction fetch accesses originating at EL0.
| EN_ALT_IPARTID_EL0 | Meaning |
|---|---|
| 0b0 |
The alternative PARTID configured in MPAM0_EL1.altPARTID is not used for generating MPAM information for instruction fetch accesses. |
| 0b1 |
The alternative PARTID configured in MPAM0_EL1.altPARTID is used for generating MPAM information for instruction fetch accesses. |
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on execution at EL0.
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name MPAMCTL_EL1 or MPAMCTL_EL12 are not guaranteed to be ordered with respect to accesses using the other accessor name.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, MPAMCTL_EL1
(op0 = 0b11, op1 = 0b000, CRn = 0b1010, CRm = 0b0101, op2 = 0b010)
if !IsFeatureImplemented(FEAT_MPAMv2) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EL2Enabled() && IsFeatureImplemented(FEAT_MPAMv2) && MPAMHCR_EL2().nTRAPMPAM1EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x918); else X{64}(t) = MPAMCTL_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = MPAMCTL_EL2(); else X{64}(t) = MPAMCTL_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = MPAMCTL_EL1(); end;
MSR MPAMCTL_EL1, <Xt>
(op0 = 0b11, op1 = 0b000, CRn = 0b1010, CRm = 0b0101, op2 = 0b010)
if !IsFeatureImplemented(FEAT_MPAMv2) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EL2Enabled() && IsFeatureImplemented(FEAT_MPAMv2) && MPAMHCR_EL2().nTRAPMPAM1EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x918) = X{64}(t); else MPAMCTL_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then MPAMCTL_EL2() = X{64}(t); else MPAMCTL_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then MPAMCTL_EL1() = X{64}(t); end;
MRS <Xt>, MPAMCTL_EL12
(op0 = 0b11, op1 = 0b101, CRn = 0b1010, CRm = 0b0101, op2 = 0b010)
if !IsFeatureImplemented(FEAT_MPAMv2) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then X{64}(t) = NVMem(0x918); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then if HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else AArch64_SystemAccessTrap(EL2, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = MPAMCTL_EL1(); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X{64}(t) = MPAMCTL_EL1(); else Undefined(); end; end;
MSR MPAMCTL_EL12, <Xt>
(op0 = 0b11, op1 = 0b101, CRn = 0b1010, CRm = 0b0101, op2 = 0b010)
if !IsFeatureImplemented(FEAT_MPAMv2) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem(0x918) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then if HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else AArch64_SystemAccessTrap(EL2, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else MPAMCTL_EL1() = X{64}(t); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then MPAMCTL_EL1() = X{64}(t); else Undefined(); end; end;
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