Returns the tracing capabilities of the trace unit.
External register TRCIDR1 bits [31:0] are architecturally mapped to AArch64 System register TRCIDR1[31:0].
This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCIDR1 are RES0.
TRCIDR1 is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DESIGNER | RES0 | RES1 | TRCARCHMAJ | TRCARCHMIN | REVISION | ||||||||||||||||||||||||||
Indicates which company designed the trace unit. The permitted values of this field are the same as MIDR_EL1.Implementer.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Reserved, RES0.
Reserved, RES1.
Major architecture version.
| TRCARCHMAJ | Meaning |
|---|---|
| 0b1111 |
If both TRCIDR1.TRCARCHMAJ and TRCIDR1.TRCARCHMIN == 0xF then refer to TRCDEVARCH. |
All other values are reserved.
This field reads as 0b1111.
Access to this field is RO.
Minor architecture version.
| TRCARCHMIN | Meaning |
|---|---|
| 0b1111 |
If both TRCIDR1.TRCARCHMAJ and TRCIDR1.TRCARCHMIN == 0xF then refer to TRCDEVARCH. |
All other values are reserved.
This field reads as 0b1111.
Access to this field is RO.
Implementation revision.
Returns an IMPLEMENTATION DEFINED value that identifies the revision of the trace unit.
Arm deprecates any use of this field and recommends that implementations set this field to zero.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
| Component | Offset | Instance |
|---|---|---|
| ETE | 0x1E4 | TRCIDR1 |
This interface is accessible as follows: