Provides discovery information for the component.
For additional information, see the CoreSight Architecture Specification.
External register TRCDEVARCH bits [31:0] are architecturally mapped to AArch64 System register TRCDEVARCH[31:0].
This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCDEVARCH are RES0.
TRCDEVARCH is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ARCHITECT | PRESENT | REVISION | ARCHVER | ARCHPART |
Architect. Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code.
ARCHITECT | Meaning |
---|---|
0b01000111011 |
JEP106 continuation code 0x4, ID code 0x3B. |
Other values are defined by the JEDEC JEP106 standard.
This field reads as 0x23B.
Access to this field is RO.
DEVARCH Present. Defines that the DEVARCH register is present.
The value of this field is an IMPLEMENTATION DEFINED choice of:
PRESENT | Meaning |
---|---|
0b0 |
Device Architecture information not present. |
0b1 |
Device Architecture information present. |
This field reads as 1.
Access to this field is RO.
Revision. Defines the architecture revision of the component.
The value of this field is an IMPLEMENTATION DEFINED choice of:
REVISION | Meaning |
---|---|
0b0000 |
ETEv1.0, FEAT_ETE. |
0b0001 |
ETEv1.1, FEAT_ETEv1p1. |
0b0010 |
ETEv1.2, FEAT_ETEv1p2. |
0b0011 |
ETEv1.3, FEAT_ETEv1p3. |
All other values are reserved.
Access to this field is RO.
Architecture Version. Defines the architecture version of the component.
ARCHVER | Meaning |
---|---|
0b0101 |
ETEv1. |
ARCHVER and ARCHPART are also defined as a single field, ARCHID, so that ARCHVER is ARCHID[15:12].
This field reads as 0x5.
Access to this field is RO.
Architecture Part. Defines the architecture of the component.
ARCHPART | Meaning |
---|---|
0xA13 |
Arm PE trace architecture. |
ARCHVER and ARCHPART are also defined as a single field, ARCHID, so that ARCHPART is ARCHID[11:0].
This field reads as 0xA13.
Access to this field is RO.
External debugger accesses to this register are unaffected by the OS Lock.
Component | Offset | Instance |
---|---|---|
ETE | 0xFBC | TRCDEVARCH |
This interface is accessible as follows: