Provides discovery information for the component.
For additional information, see the CoreSight Architecture Specification.
AArch64 System register TRCDEVARCH bits [31:0] are architecturally mapped to External register TRCDEVARCH[31:0].
This register is present only when FEAT_ETE is implemented and System register access to the trace unit registers is implemented. Otherwise, direct accesses to TRCDEVARCH are UNDEFINED.
TRCDEVARCH is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| ARCHITECT | PRESENT | REVISION | ARCHVER | ARCHPART | |||||||||||||||||||||||||||
Reserved, RES0.
Architect. Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code.
| ARCHITECT | Meaning |
|---|---|
| 0b01000111011 |
JEP106 continuation code 0x4, ID code 0x3B. |
Other values are defined by the JEDEC JEP106 standard.
This field reads as 0x23B.
Access to this field is RO.
DEVARCH Present. Defines that the DEVARCH register is present.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| PRESENT | Meaning |
|---|---|
| 0b0 |
Device Architecture information not present. |
| 0b1 |
Device Architecture information present. |
This field reads as 1.
Access to this field is RO.
Revision. Defines the architecture revision of the component.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| REVISION | Meaning |
|---|---|
| 0b0000 |
ETEv1.0, FEAT_ETE. |
| 0b0001 |
ETEv1.1, FEAT_ETEv1p1. |
| 0b0010 |
ETEv1.2, FEAT_ETEv1p2. |
| 0b0011 |
ETEv1.3, FEAT_ETEv1p3. |
All other values are reserved.
Access to this field is RO.
Architecture Version. Defines the architecture version of the component.
| ARCHVER | Meaning |
|---|---|
| 0b0101 |
ETEv1. |
ARCHVER and ARCHPART are also defined as a single field, ARCHID, so that ARCHVER is ARCHID[15:12].
This field reads as 0x5.
Access to this field is RO.
Architecture Part. Defines the architecture of the component.
| ARCHPART | Meaning |
|---|---|
| 0xA13 |
Arm PE trace architecture. |
ARCHVER and ARCHPART are also defined as a single field, ARCHID, so that ARCHPART is ARCHID[11:0].
This field reads as 0xA13.
Access to this field is RO.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, TRCDEVARCH
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b10 | 0b001 | 0b0111 | 0b1111 | 0b110 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.TTA == '1' then UNDEFINED; elsif CPACR_EL1.TTA == '1' then AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.TRCID == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR2.TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X[t, 64] = TRCDEVARCH; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.TTA == '1' then UNDEFINED; elsif CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif !ELUsingAArch32(EL1) && IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR2.TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X[t, 64] = TRCDEVARCH; elsif PSTATE.EL == EL3 then if CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); elsif !ELUsingAArch32(EL1) && IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR2.TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X[t, 64] = TRCDEVARCH;