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TCR2_EL2: Extended Translation Control Register (EL2)

Purpose

The control register for stage 1 of the EL2&0 translation regime.

Configuration

This register is present only when FEAT_TCR2 is implemented. Otherwise, direct accesses to TCR2_EL2 are UNDEFINED.

If EL2 is not implemented, this register is RES0 from EL3.

Attributes

TCR2_EL2 is a 64-bit register.

Field descriptions

When the Effective value of HCR_EL2.E2H is not 1:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0AMEC0HAFTPTTWIRES0AIEPOERES0PIEPnCH

Unless stated otherwise, all the bits in TCR2_EL2 are permitted to be cached in a TLB.

Bits [63:13]

Reserved, RES0.

AMEC0, bit [12]

When FEAT_MEC is implemented:

This field controls the enabling of the Alternate MECID translations for the EL2 translation regime.

TCR2_EL2.AMEC0 is provided to enable the safe update of MECID_A0_EL2, by disabling access and speculation to AMEC==1 Block or Page descriptors during the update.

AMEC0Meaning
0b0

Use of a Block or Page descriptor containing AMEC == 1 generates a Translation fault.

0b1

Accesses translated by a Block or Page descriptor containing AMEC == 1 are associated with the MECID configured in MECID_A0_EL2.

This bit is permitted to be cached in a TLB only if it is 1.

This field is ignored by the PE and treated as zero when EL3 is implemented and SCR_EL3.TCR2En == 0.

When SCTLR2_EL2.EMEC is 0, this field is ignored by the PE and the bit position of AMEC is RES0 in Block and Page descriptors.

The reset behavior of this field is:

Accessing this field has the following behavior:



Otherwise:

Reserved, RES0.

HAFT, bit [11]

When FEAT_HAFT is implemented:

Hardware managed Access Flag for Table descriptors.

Enables the Hardware managed Access Flag for Table descriptors.

HAFTMeaning
0b0

Hardware managed Access Flag for Table descriptors is disabled.

0b1

Hardware managed Access Flag for Table descriptors is enabled.

This field is ignored by the PE and treated as zero when EL3 is implemented and SCR_EL3.TCR2En == 0.

The reset behavior of this field is:



Otherwise:

Reserved, RES0.

PTTWI, bit [10]

When FEAT_THE is implemented:

Permit Translation table walk Incoherence.

Permits RCWS instructions to generate writes that have the Reduced Coherence property.

PTTWIMeaning
0b0

Write accesses generated by RCWS at EL2 or EL2&0 do not have the Reduced Coherence property.

0b1

Write accesses generated by RCWS at EL2 or EL2&0 have the Reduced Coherence property.

This bit is permitted to be implemented as a read-only bit with a fixed value of 0.

This field is ignored by the PE and treated as zero when EL3 is implemented and SCR_EL3.TCR2En == 0.

The reset behavior of this field is:



Otherwise:

Reserved, RES0.

Bits [9:5]

Reserved, RES0.

AIE, bit [4]

When FEAT_AIE is implemented:

Enable Attribute Indexing Extension.

AIEMeaning
0b0

Attribute Indexing Extension Disabled.

0b1

Attribute Indexing Extension Enabled.

This field is ignored by the PE and treated as zero when EL3 is implemented and SCR_EL3.TCR2En == 0.

The reset behavior of this field is:



Otherwise:

Reserved, RES0.

POE, bit [3]

When FEAT_S1POE is implemented:

Enables Permission Overlay for EL2 accesses.

POEMeaning
0b0

Permission overlay disabled for EL2 access in stage 1 of EL2 translation regime.

0b1

Permission overlay enabled for EL2 access in stage 1 of EL2 translation regime.

This bit is not permitted to be cached in a TLB.

This field is ignored by the PE and treated as zero when EL3 is implemented and SCR_EL3.TCR2En == 0.

The reset behavior of this field is:



Otherwise:

Reserved, RES0.

Bit [2]

Reserved, RES0.

PIE, bit [1]

When FEAT_S1PIE is implemented:

Enables usage of Indirect Permission Scheme.

PIEMeaning
0b0

Direct permission model.

0b1

Indirect permission model.

This field is ignored by the PE and treated as zero when EL3 is implemented and SCR_EL3.TCR2En == 0.

The reset behavior of this field is:



Otherwise:

Reserved, RES0.

PnCH, bit [0]

When FEAT_THE is implemented:

Protected attribute enable.Indicates use of bit[52] of the stage 1 translation table entry.

PnCHMeaning
0b0

Bit[52] of each stage 1 translation table entry does not indicate protected attribute.

0b1

Bit[52] of each stage 1 translation table entry indicates protected attribute.

This field is ignored by the PE and treated as zero when EL3 is implemented and SCR_EL3.TCR2En == 0.

The reset behavior of this field is:



Otherwise:

Reserved, RES0.

When the Effective value of HCR_EL2.E2H is 1:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0FNG1FNG0A2DisCH1DisCH0AMEC1AMEC0HAFTPTTWISKL1SKL0D128AIEPOEE0POEPIEPnCH

Unless stated otherwise, all the bits in TCR2_EL2 are permitted to be cached in a TLB.

Bits [63:19]

Reserved, RES0.

FNG1, bit [18]

When FEAT_ASID2 is implemented:

Force non-global translations for TTBR1_EL2.

FNG1Meaning
0b0

This bit has no effect on the interpretation of the nG bit.

0b1

Translations are treated as non-global regardless of the value of the nG bit.

This bit is permitted to be cached in a TLB.

This field is ignored by the PE and treated as zero when EL3 is implemented and SCR_EL3.TCR2En == 0.

The reset behavior of this field is:



Otherwise:

Reserved, RES0.

FNG0, bit [17]

When FEAT_ASID2 is implemented:

Force non-global translations for TTBR0_EL2.

FNG0Meaning
0b0

This bit has no effect on the interpretation of the nG bit.

0b1

Translations are treated as non-global regardless of the value of the nG bit.

This bit is permitted to be cached in a TLB.

This field is ignored by the PE and treated as zero when EL3 is implemented and SCR_EL3.TCR2En == 0.

The reset behavior of this field is:



Otherwise:

Reserved, RES0.

A2, bit [16]

When FEAT_ASID2 is implemented:

Enable use of two ASIDs.

A2Meaning
0b0

Use of two ASIDs is disabled.

0b1

Use of two ASIDs is enabled.

This bit is permitted to be cached in a TLB.

This field is ignored by the PE and treated as zero when EL3 is implemented and SCR_EL3.TCR2En == 0.

The reset behavior of this field is:



Otherwise:

Reserved, RES0.

DisCH1, bit [15]

When FEAT_D128 is implemented and TCR2_EL2.D128 == 1:

Disable the Contiguous bit for the Start Table for TTBR1_EL2.

DisCH1Meaning
0b0

The Contiguous bit of Block or Page descriptors of the Start Table for TTBR1_EL2 is not affected by this field.

0b1

The Contiguous bit of Block or Page descriptors of the Start Table for TTBR1_EL2 is treated as 0.

This field is ignored by the PE and treated as zero when EL3 is implemented and SCR_EL3.TCR2En == 0.

The reset behavior of this field is:



Otherwise:

Reserved, RES0.

DisCH0, bit [14]

When FEAT_D128 is implemented and TCR2_EL2.D128 == 1:

Disable the Contiguous bit for the Start Table for TTBR0_EL2.

DisCH0Meaning
0b0

The Contiguous bit of Block or Page descriptors of the Start Table for TTBR0_EL2 is not affected by this field.

0b1

The Contiguous bit of Block or Page descriptors of the Start Table for TTBR0_EL2 is treated as 0.

This field is ignored by the PE and treated as zero when EL3 is implemented and SCR_EL3.TCR2En == 0.

The reset behavior of this field is:



Otherwise:

Reserved, RES0.

AMEC1, bit [13]

When FEAT_MEC is implemented:

This field controls the enabling of the Alternate MECID translations for accesses in the TTBR1_EL2 half of the VA range, for the EL2&0 translation regime.

TCR2_EL2.AMEC1 is provided to enable the safe update of MECID_A1_EL2, by disabling access and speculation to AMEC == 1 Block or Page descriptors during the update.

AMEC1Meaning
0b0

Use of a Block or Page descriptor containing AMEC == 1 generates a Translation fault.

0b1

Accesses translated by a Block or Page descriptor containing AMEC == 1 are associated with the MECID configured in MECID_A1_EL2.

This bit is permitted to be cached in a TLB only if it is 1.

This field is ignored by the PE and treated as zero when EL3 is implemented and SCR_EL3.TCR2En == 0.

When SCTLR2_EL2.EMEC is 0, this field is ignored by the PE and the bit position of AMEC is RES0 in Block and Page descriptors.

The reset behavior of this field is:

Accessing this field has the following behavior:



Otherwise:

Reserved, RES0.

AMEC0, bit [12]

When FEAT_MEC is implemented:

This field controls the enabling of the Alternate MECID translations for accesses in the TTBR0_EL2 half of the VA range, for the EL2&0 translation regime.

TCR2_EL2.AMEC0 is provided to enable the safe update of MECID_A0_EL2, by disabling access and speculation to AMEC==1 Block or Page descriptors during the update.

AMEC0Meaning
0b0

Use of a Block or Page descriptor containing AMEC == 1 generates a Translation fault.

0b1

Accesses translated by a Block or Page descriptor containing AMEC == 1 are associated with the MECID configured in MECID_A0_EL2.

This bit is permitted to be cached in a TLB only if it is 1.

This field is ignored by the PE and treated as zero when EL3 is implemented and SCR_EL3.TCR2En == 0.

When SCTLR2_EL2.EMEC is 0, this field is ignored by the PE and the bit position of AMEC is RES0 in Block and Page descriptors.

The reset behavior of this field is:

Accessing this field has the following behavior:



Otherwise:

Reserved, RES0.

HAFT, bit [11]

When FEAT_HAFT is implemented:

Hardware managed Access Flag for Table descriptors.

Enables the Hardware managed Access Flag for Table descriptors.

HAFTMeaning
0b0

Hardware managed Access Flag for Table descriptors is disabled.

0b1

Hardware managed Access Flag for Table descriptors is enabled.

This field is ignored by the PE and treated as zero when EL3 is implemented and SCR_EL3.TCR2En == 0.

The reset behavior of this field is:



Otherwise:

Reserved, RES0.

PTTWI, bit [10]

When FEAT_THE is implemented:

Permit Translation table walk Incoherence.

Permits RCWS instructions to generate writes that have the Reduced Coherence property.

PTTWIMeaning
0b0

Write accesses generated by RCWS do not have the Reduced Coherence property.

0b1

Write accesses generated by RCWS have the Reduced Coherence property.

This bit is permitted to be implemented as a read-only bit with a fixed value of 0.

This field is ignored by the PE and treated as zero when EL3 is implemented and SCR_EL3.TCR2En == 0.

The reset behavior of this field is:



Otherwise:

Reserved, RES0.

SKL1, bits [9:8]

When FEAT_D128 is implemented:

Skip Level associated with translation table walks using TTBR1_EL2.

This determines the number of levels to be skipped in the regular start level of the stage 1 EL2&0 translation table walks using TTBR1_EL2.

SKL1Meaning
0b00

Skip 0 level in the regular start level.

0b01

Skip 1 level in the regular start level.

0b10

Skip 2 levels in the regular start level.

0b11

Skip 3 levels in the regular start level.

This field is IGNORED when TCR2_EL2.D128 is 0.

This field is ignored by the PE and treated as zero when EL3 is implemented and SCR_EL3.TCR2En == 0.

The reset behavior of this field is:



Otherwise:

Reserved, RES0.

SKL0, bits [7:6]

When FEAT_D128 is implemented:

Skip Level associated with translation table walks using TTBR0_EL2.

This determines the number of levels to be skipped in the regular start level of the stage 1 EL2&0 translation table walks using TTBR0_EL2.

SKL0Meaning
0b00

Skip 0 level in the regular start level.

0b01

Skip 1 level in the regular start level.

0b10

Skip 2 levels in the regular start level.

0b11

Skip 3 levels in the regular start level.

This field is IGNORED when TCR2_EL2.D128 is 0.

This field is ignored by the PE and treated as zero when EL3 is implemented and SCR_EL3.TCR2En == 0.

The reset behavior of this field is:



Otherwise:

Reserved, RES0.

D128, bit [5]

When FEAT_D128 is implemented:

Enables VMSAv9-128 translation system.

D128Meaning
0b0

Translation system follows VMSA-64 translation process.

0b1

Translation system follows VMSAv9-128 translation process.

This field is IGNORED when TCR2_EL2.D128 is 0.

This field is ignored by the PE and treated as zero when EL3 is implemented and SCR_EL3.TCR2En == 0.

The reset behavior of this field is:



Otherwise:

Reserved, RES0.

AIE, bit [4]

When FEAT_AIE is implemented:

Enable Attribute Indexing Extension.

AIEMeaning
0b0

Attribute Indexing Extension Disabled.

0b1

Attribute Indexing Extension Enabled.

This field is RES1 when TCR2_EL2.D128 is 1.

This field is ignored by the PE and treated as zero when EL3 is implemented and SCR_EL3.TCR2En == 0.

The reset behavior of this field is:



Otherwise:

Reserved, RES0.

POE, bit [3]

When FEAT_S1POE is implemented:

Enables Permission Overlay for privileged accesses from EL2&0 translation regime.

POEMeaning
0b0

Permission overlay disabled for EL2 access in stage 1 of EL2&0 translation regime.

0b1

Permission overlay enabled for EL2 access in stage 1 of EL2&0 translation regime.

This bit is not permitted to be cached in a TLB.

This field is ignored by the PE and treated as zero when EL3 is implemented and SCR_EL3.TCR2En == 0.

The reset behavior of this field is:



Otherwise:

Reserved, RES0.

E0POE, bit [2]

When FEAT_S1POE is implemented:

Enables Permission Overlay for unprivileged accesses from EL2&0 translation regime.

E0POEMeaning
0b0

Permission overlay disabled for EL0 access in stage 1 of EL2&0 translation regime.

0b1

Permission overlay enabled for EL0 access in stage 1 of EL2&0 translation regime.

This bit is not permitted to be cached in a TLB.

This field is ignored by the PE and treated as zero when EL3 is implemented and SCR_EL3.TCR2En == 0.

The reset behavior of this field is:



Otherwise:

Reserved, RES0.

PIE, bit [1]

When FEAT_S1PIE is implemented:

Enables usage of Indirect Permission Scheme.

PIEMeaning
0b0

Direct permission model.

0b1

Indirect permission model.

This field is RES1 when TCR2_EL2.D128 is 1.

This field is ignored by the PE and treated as zero when EL3 is implemented and SCR_EL3.TCR2En == 0.

The reset behavior of this field is:



Otherwise:

Reserved, RES0.

PnCH, bit [0]

When FEAT_THE is implemented:

Protected attribute enable.Indicates use of bit[52] of the stage 1 translation table entry.

PnCHMeaning
0b0

Bit[52] of each stage 1 translation table entry does not indicate protected attribute.

0b1

Bit[52] of each stage 1 translation table entry indicate protected attribute.

This field is RES1 when TCR2_EL2.D128 is 1.

This field is ignored by the PE and treated as zero when EL3 is implemented and SCR_EL3.TCR2En == 0.

The reset behavior of this field is:



Otherwise:

Reserved, RES0.

Accessing TCR2_EL2

When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL2 using the register name TCR2_EL2 or TCR2_EL1 are not guaranteed to be ordered with respect to accesses using the other register name.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, TCR2_EL2

op0op1CRnCRmop2
0b110b1000b00100b00000b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.TCR2En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.TCR2En == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = TCR2_EL2; elsif PSTATE.EL == EL3 then X[t, 64] = TCR2_EL2;

MSR TCR2_EL2, <Xt>

op0op1CRnCRmop2
0b110b1000b00100b00000b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.TCR2En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.TCR2En == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else TCR2_EL2 = X[t, 64]; elsif PSTATE.EL == EL3 then TCR2_EL2 = X[t, 64];

MRS <Xt>, TCR2_EL1

op0op1CRnCRmop2
0b110b0000b00100b00000b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.TCR2En == '0' then UNDEFINED; elsif EL2Enabled() && HCR_EL2.TRVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.TCR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2.TCR2En == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.TCR2En == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectiveHCR_EL2_NVx() == '111' then X[t, 64] = NVMem[0x270]; else X[t, 64] = TCR2_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.TCR2En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.TCR2En == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif ELIsInHost(EL2) then X[t, 64] = TCR2_EL2; else X[t, 64] = TCR2_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = TCR2_EL1;

MSR TCR2_EL1, <Xt>

op0op1CRnCRmop2
0b110b0000b00100b00000b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.TCR2En == '0' then UNDEFINED; elsif EL2Enabled() && HCR_EL2.TVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGWTR_EL2.TCR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2.TCR2En == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.TCR2En == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectiveHCR_EL2_NVx() == '111' then NVMem[0x270] = X[t, 64]; else TCR2_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.TCR2En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.TCR2En == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif ELIsInHost(EL2) then TCR2_EL2 = X[t, 64]; else TCR2_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then TCR2_EL1 = X[t, 64];