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MECID_A0_EL2: Alternate MECID for EL2 and EL2&0 translation regimes

Purpose

Alternate MECID for EL2 and EL2&0 accesses translated by TTBR0_EL2.

Configuration

This register is present only when FEAT_MEC is implemented. Otherwise, direct accesses to MECID_A0_EL2 are UNDEFINED.

If EL2 is not implemented, this register is RES0 from EL3.

Attributes

MECID_A0_EL2 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0MECID

Bits [63:16]

Reserved, RES0.

MECID, bits [15:0]

If MECIDWidth is less than 16 bits, bits[15:MECIDWidth] are RES0.

Note

MECIDWidth is defined in MECIDR_EL2.MECIDWidthm1.

The reset behavior of this field is:

Accessing MECID_A0_EL2

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, MECID_A0_EL2

op0op1CRnCRmop2
0b110b1000b10100b10000b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then if !IsCurrentSecurityState(SS_Realm) then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.MECEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.MECEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = MECID_A0_EL2; elsif PSTATE.EL == EL3 then X[t, 64] = MECID_A0_EL2;

MSR MECID_A0_EL2, <Xt>

op0op1CRnCRmop2
0b110b1000b10100b10000b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then if !IsCurrentSecurityState(SS_Realm) then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.MECEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.MECEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else MECID_A0_EL2 = X[t, 64]; elsif PSTATE.EL == EL3 then MECID_A0_EL2 = X[t, 64];