Provides information about the instruction sets implemented by the PE in AArch32 state.
Must be interpreted with ID_ISAR0_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1, ID_ISAR4_EL1, and ID_ISAR5_EL1.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'.
AArch64 System register ID_ISAR1_EL1 bits [31:0] are architecturally mapped to AArch32 System register ID_ISAR1[31:0].
ID_ISAR1_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| Jazelle | Interwork | Immediate | IfThen | Extend | Except_AR | Except | Endian | ||||||||||||||||||||||||
Reserved, RES0.
Indicates the implemented Jazelle extension instructions.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| Jazelle | Meaning |
|---|---|
| 0b0000 |
No support for Jazelle. |
| 0b0001 |
Adds the BXJ instruction and the J bit in the PSR. This setting might indicate a trivial implementation of the Jazelle extension. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0001.
Access to this field is RO.
Indicates the implemented Interworking instructions.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| Interwork | Meaning |
|---|---|
| 0b0000 |
None implemented. |
| 0b0001 |
Adds the BX instruction, and the T bit in the PSR. |
| 0b0010 |
As for 0b0001, and adds the BLX instruction. PC loads have BX-like behavior. |
| 0b0011 |
As for 0b0010, and guarantees that data-processing instructions in the A32 instruction set with the PC as the destination and the S bit clear have BX-like behavior. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0011.
Access to this field is RO.
Indicates the implemented data-processing instructions with long immediates.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| Immediate | Meaning |
|---|---|
| 0b0000 |
None implemented. |
| 0b0001 | Adds:
|
All other values are reserved.
In Armv8-A, the only permitted value is 0b0001.
Access to this field is RO.
Indicates the implemented If-Then instructions in the T32 instruction set.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| IfThen | Meaning |
|---|---|
| 0b0000 |
None implemented. |
| 0b0001 |
Adds the IT instructions, and the IT bits in the PSRs. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0001.
Access to this field is RO.
Indicates the implemented Extend instructions.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| Extend | Meaning |
|---|---|
| 0b0000 |
No scalar sign-extend or zero-extend instructions are implemented, where scalar instructions means non-Advanced SIMD instructions. |
| 0b0001 |
Adds the SXTB, SXTH, UXTB, and UXTH instructions. |
| 0b0010 |
As for 0b0001, and adds the SXTB16, SXTAB, SXTAB16, SXTAH, UXTB16, UXTAB, UXTAB16, and UXTAH instructions. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0010.
Access to this field is RO.
Indicates the implemented A and R-profile exception-handling instructions.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| Except_AR | Meaning |
|---|---|
| 0b0000 |
None implemented. |
| 0b0001 |
Adds the SRS and RFE instructions, and the A and R-profile forms of the CPS instruction. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0001.
Access to this field is RO.
Indicates the implemented exception-handling instructions in the A32 instruction set.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| Except | Meaning |
|---|---|
| 0b0000 |
Not implemented. This indicates that the User bank and Exception return forms of the LDM and STM instructions are not implemented. |
| 0b0001 |
Adds the LDM (exception return), LDM (user registers), and STM (user registers) instruction versions. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0001.
Access to this field is RO.
Indicates the implemented Endian instructions.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| Endian | Meaning |
|---|---|
| 0b0000 |
None implemented. |
| 0b0001 |
Adds the SETEND instruction, and the E bit in the PSRs. |
All other values are reserved.
In Armv8-A, the permitted values are 0b0000 and 0b0001.
Access to this field is RO.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| UNKNOWN | |||||||||||||||||||||||||||||||
| UNKNOWN | |||||||||||||||||||||||||||||||
Reserved, UNKNOWN.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, ID_ISAR1_EL1
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b0000 | 0b0010 | 0b001 |
if PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = ID_ISAR1_EL1; elsif PSTATE.EL == EL2 then X[t, 64] = ID_ISAR1_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = ID_ISAR1_EL1;