Provides information about the instruction sets implemented by the PE in AArch32 state.
Must be interpreted with ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1, ID_ISAR4_EL1, and ID_ISAR5_EL1.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'.
AArch64 System register ID_ISAR0_EL1 bits [31:0] are architecturally mapped to AArch32 System register ID_ISAR0[31:0].
ID_ISAR0_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | Divide | Debug | Coproc | CmpBranch | BitField | BitCount | Swap | ||||||||||||||||||||||||
Reserved, RES0.
Indicates the implemented Divide instructions.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| Divide | Meaning |
|---|---|
| 0b0000 |
None implemented. |
| 0b0001 |
Adds SDIV and UDIV in the T32 instruction set. |
| 0b0010 |
As for 0b0001, and adds SDIV and UDIV in the A32 instruction set. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0010.
Access to this field is RO.
Indicates the implemented Debug instructions.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| Debug | Meaning |
|---|---|
| 0b0000 |
None implemented. |
| 0b0001 |
Adds BKPT. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0001.
Access to this field is RO.
Indicates the implemented System register access instructions.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| Coproc | Meaning |
|---|---|
| 0b0000 |
None implemented, except for instructions separately attributed by the architecture to provide access to AArch32 System registers and System instructions. |
| 0b0001 |
Adds generic CDP, LDC, MCR, MRC, and STC. |
| 0b0010 |
As for 0b0001, and adds generic CDP2, LDC2, MCR2, MRC2, and STC2. |
| 0b0011 |
As for 0b0010, and adds generic MCRR and MRRC. |
| 0b0100 |
As for 0b0011, and adds generic MCRR2 and MRRC2. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0000.
Access to this field is RO.
Indicates the implemented combined Compare and Branch instructions in the T32 instruction set.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| CmpBranch | Meaning |
|---|---|
| 0b0000 |
None implemented. |
| 0b0001 |
Adds CBNZ and CBZ. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0001.
Access to this field is RO.
Indicates the implemented BitField instructions.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| BitField | Meaning |
|---|---|
| 0b0000 |
None implemented. |
| 0b0001 |
Adds BFC, BFI, SBFX, and UBFX. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0001.
Access to this field is RO.
Indicates the implemented Bit Counting instructions.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| BitCount | Meaning |
|---|---|
| 0b0000 |
None implemented. |
| 0b0001 |
Adds CLZ. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0001.
Access to this field is RO.
Indicates the implemented Swap instructions in the A32 instruction set.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| Swap | Meaning |
|---|---|
| 0b0000 |
None implemented. |
| 0b0001 |
Adds SWP and SWPB. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0000.
Access to this field is RO.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| UNKNOWN | |||||||||||||||||||||||||||||||
| UNKNOWN | |||||||||||||||||||||||||||||||
Reserved, UNKNOWN.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, ID_ISAR0_EL1
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b0000 | 0b0010 | 0b000 |
if PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = ID_ISAR0_EL1; elsif PSTATE.EL == EL2 then X[t, 64] = ID_ISAR0_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = ID_ISAR0_EL1;