Adds to the information given by the DBGDIDR by describing other features of the debug implementation.
This register is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to DBGDEVID are UNDEFINED.
This register is required in all implementations.
DBGDEVID is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CIDMask | AuxRegs | DoubleLock | VirtExtns | VectorCatch | BPAddrMask | WPAddrMask | PCSample | ||||||||||||||||||||||||
Indicates the level of support for the Context ID matching breakpoint masking capability. Defined values are:
| CIDMask | Meaning |
|---|---|
| 0b0000 |
Context ID masking is not implemented. |
| 0b0001 |
Context ID masking is implemented. |
All other values are reserved. The value of this for Armv8 is 0b0000.
Indicates support for Auxiliary registers. Permitted values for this field are:
| AuxRegs | Meaning |
|---|---|
| 0b0000 |
None supported. |
| 0b0001 |
Support for External Debug Auxiliary Control Register, EDACR. |
All other values are reserved.
OS Double Lock implemented. Defined values are:
| DoubleLock | Meaning |
|---|---|
| 0b0000 |
OS Double Lock is not implemented. DBGOSDLR is RAZ/WI. |
| 0b0001 |
OS Double Lock is implemented. DBGOSDLR is RW. |
FEAT_DoubleLock implements the functionality identified by the value 0b0001.
All other values are reserved.
Indicates whether EL2 is implemented. Defined values are:
| VirtExtns | Meaning |
|---|---|
| 0b0000 |
EL2 is not implemented. |
| 0b0001 |
EL2 is implemented. |
All other values are reserved.
Defines the form of Vector Catch exception implemented. Defined values are:
| VectorCatch | Meaning |
|---|---|
| 0b0000 |
Address matching Vector Catch exception implemented. |
| 0b0001 |
Exception matching Vector Catch exception implemented. |
All other values are reserved.
Indicates the level of support for the instruction address matching breakpoint masking capability. Defined values are:
| BPAddrMask | Meaning |
|---|---|
| 0b0000 |
Breakpoint address masking might be implemented. If not implemented, DBGBCR<n>[28:24] is RAZ/WI. |
| 0b0001 |
Breakpoint address masking is implemented. |
| 0b1111 |
Breakpoint address masking is not implemented. DBGBCR<n>[28:24] is RES0. |
All other values are reserved. The value of this for Armv8 is 0b1111.
Indicates the level of support for the data address matching watchpoint masking capability. Defined values are:
| WPAddrMask | Meaning |
|---|---|
| 0b0000 |
Watchpoint address masking might be implemented. If not implemented, DBGWCR<n>.MASK (Address mask) is RAZ/WI. |
| 0b0001 |
Watchpoint address masking is implemented. |
| 0b1111 |
Watchpoint address masking is not implemented. DBGWCR<n>.MASK (Address mask) is RES0. |
All other values are reserved. The value of this for Armv8 is 0b0001.
Indicates the level of PC Sample-based Profiling support using external debug registers. Defined values are:
| PCSample | Meaning |
|---|---|
| 0b0000 |
PC Sample-based Profiling Extension is not implemented in the external debug registers space. |
| 0b0010 |
Only EDPCSR and EDCIDSR are implemented. This option is only permitted if EL3 and EL2 are not implemented. |
| 0b0011 |
All other values are reserved.
When FEAT_PCSRv8p2 is implemented, the only permitted value is 0b0000.
FEAT_PCSRv8p2 implements the PC Sample-based Profiling Extension in the Performance Monitors register space, as indicated by the value of PMU.PMDEVID.PCSample.
Accesses to this register use the following encodings in the System register encoding space:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1110 | 0b000 | 0b0111 | 0b0010 | 0b111 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.<TDE,TDA> != '00' then AArch32.TakeHypTrapException(0x05); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x05); else R[t] = DBGDEVID; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x05); else R[t] = DBGDEVID; elsif PSTATE.EL == EL3 then R[t] = DBGDEVID;