Specifies which version of the Debug architecture is implemented, and some features of the debug implementation.
This register is present only when AArch32 is supported. Otherwise, direct accesses to DBGDIDR are UNDEFINED.
If EL1 cannot use AArch32 then the implementation of this register is OPTIONAL and deprecated.
DBGDIDR is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| WRPs | BRPs | CTX_CMPs | Version | RES1 | nSUHD_imp | RES0 | SE_imp | RES0 | |||||||||||||||||||||||
Number of watchpoints, minus 1.
| WRPs | Meaning |
|---|---|
| 0b0001..0b1111 |
The number of watchpoints, minus 1. |
If FEAT_Debugv8p9 is implemented and 16 or more watchpoints are implemented, this field reads as 0b1111.
If AArch32 is supported at EL1, then the PE does not implement more than 16 watchpoints.
The value 0b0000 is reserved.
Number of breakpoints, minus 1.
| BRPs | Meaning |
|---|---|
| 0b0001..0b1111 |
The number of breakpoints, minus 1. |
If FEAT_Debugv8p9 is implemented and 16 or more breakpoints are implemented, this field reads as 0b1111.
If AArch32 is supported at EL1, then the PE does not implement more than 16 breakpoints.
The value 0b0000 is reserved.
Number of context-aware breakpoints, minus 1.
| CTX_CMPs | Meaning |
|---|---|
| 0b0000..0b1111 |
The number of context-aware breakpoints, minus 1. |
The value of this field is never greater than DBGDIDR.BRPs.
If FEAT_Debugv8p9 is implemented and 16 or more context-aware breakpoints are implemented, this field reads as 0b1111.
If AArch32 is supported at EL1, then the PE does not implement more than 16 breakpoints.
Debug architecture version. Indicates presence of Armv8 debug architecture. Defined values are:
| Version | Meaning |
|---|---|
| 0b0000 |
Not supported. |
| 0b0001 |
Armv6, v6 Debug architecture, with System registers access. |
| 0b0010 |
Armv6, v6.1 Debug architecture, with System registers access. |
| 0b0011 |
Armv7, v7 Debug architecture, with only baseline System registers. |
| 0b0100 |
Armv7, v7 Debug architecture, with all System registers implemented. |
| 0b0101 |
Armv7, v7.1 Debug architecture, with System registers access. |
| 0b0110 |
Armv8.0 debug architecture. |
| 0b0111 |
Armv8.0 debug architecture with Virtualization Host Extensions. |
| 0b1000 |
Armv8.2 debug architecture, FEAT_Debugv8p2. |
| 0b1001 |
Armv8.4 debug architecture, FEAT_Debugv8p4. |
| 0b1010 |
Armv8.8 debug architecture, FEAT_Debugv8p8. |
| 0b1011 |
Armv8.9 debug architecture, FEAT_Debugv8p9. |
All other values are reserved.
From Armv8.0, the values 0b0000, 0b0001, 0b0010, 0b0011, 0b0100, and 0b0101 are not permitted.
FEAT_VHE implements the functionality identified by the value 0b0111.
FEAT_Debugv8p2 implements the functionality identified by the value 0b1000.
FEAT_Debugv8p4 implements the functionality identified by the value 0b1001.
FEAT_Debugv8p8 implements the functionality identified by the value 0b1010.
FEAT_Debugv8p9 implements the functionality identified by the value 0b1011.
From Armv8.1, when FEAT_VHE is implemented the value 0b0110 is not permitted.
From Armv8.2, the values 0b0110 and 0b0111 are not permitted.
From Armv8.4, the value 0b1000 is not permitted.
From Armv8.8, the value 0b1001 is not permitted.
From Armv8.9, the value 0b1010 is not permitted.
Reserved, RES1.
Previously indicated that Secure User Halting Debug is not implemented.
The value of this bit must match the value of the SE_imp bit.
Reserved, RES0.
EL3 implemented. The meanings of the values of this bit are:
| SE_imp | Meaning |
|---|---|
| 0b0 |
EL3 not implemented. |
| 0b1 |
EL3 implemented. |
The value of this bit must match the value of the nSUHD_imp bit.
Reserved, RES0.
Arm deprecates any access to this register from EL0.
Accesses to this register use the following encodings in the System register encoding space:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1110 | 0b000 | 0b0000 | 0b0000 | 0b000 |
if Halted() && ConstrainUnpredictableBool(Unpredictable_IGNORETRAPINDEBUG) then R[t] = DBGDIDR; elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then UNDEFINED; elsif !ELUsingAArch32(EL1) && MDSCR_EL1.TDCC == '1' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); else AArch64.AArch32SystemAccessTrap(EL1, 0x05); elsif ELUsingAArch32(EL1) && DBGDSCRext.UDCCdis == '1' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TGE == '1' then AArch32.TakeHypTrapException(0x00); else UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && (HCR_EL2.TGE == '1' || MDCR_EL2.<TDE,TDA> != '00') then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && (HCR.TGE == '1' || HDCR.<TDE,TDA> != '00') then AArch32.TakeHypTrapException(0x05); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x05); else R[t] = DBGDIDR; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.<TDE,TDA> != '00' then AArch32.TakeHypTrapException(0x05); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x05); else R[t] = DBGDIDR; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x05); else R[t] = DBGDIDR; elsif PSTATE.EL == EL3 then R[t] = DBGDIDR;