PMPIDR2

This register is present only when FEAT_PMUv3_EXT is implemented and FEAT_PMU_PIDR is implemented. Otherwise, direct accesses to PMPIDR2 are RES0.

If FEAT_DoPD is implemented, this register is in the Core power domain. If FEAT_DoPD is not implemented, this register is in the Debug power domain.

Attributes

Field descriptions

Bits [31:8]:

REVISION, bits [7:4]:

Indicates either the revision of the component, or a portion of the part number of the component.

Where the component has a single 4-bit revision number, the revision number is an incremental value starting at zero for the first revision of the component.

Where the component has separate major and minor revision numbers, the major and minor revision numbers are each incremental values starting at zero for the first revision of the component. For each minor revision of the component, the minor revision number increments monotonically. For each major revision of the component, the major revision number increments monotonically and the minor revision begins again at zero.

For a component with a 12-bit part number with a single 4-bit revision number:

PMPIDR2.REVISION indicates the 4-bit revision number.
PMPIDR3.REVAND indicates component modifications.

For a component with a 12-bit part number with separate major and minor revision numbers:

PMPIDR2.REVISION indicates the 4-bit major revision number.
PMPIDR3.REVAND indicates the 4-bit minor revision number.

For a component with a 16-bit part number:

PMPIDR2.REVISION contains part number bits [3:0].
PMPIDR3.REVAND indicates the 4-bit revision number.

The choice of which style of revision information is used is specific to the designer of the component, and might also be specific to each individual component with a different part number.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

JEDEC, bit [3]:

JEDEC-assigned JEP106 implementer code is used.

Reads as 0b1.

Access to this field is RO.

DES_1, bits [2:0]:

Designer, JEP106 identification code, bits [6:4].

The JEP106 identification and continuation codes are stored as follows:

PMPIDR1.DES_0: JEP106 identification code bits[3:0].
PMPIDR2.DES_1: JEP106 identification code bits[6:4].
PMPIDR4.DES_2: JEP106 continuation code.

These codes indicate the designer of the component and not the implementer, except where the two are the same. To obtain a number, or to see the assignment of these codes, contact JEDEC http://www.jedec.org.

A JEP106 identification and continuation code takes the following form:

A sequence of zero or more numbers, all having the value 0x7F.
A following 8-bit number, that is not 0x7F, and where bit[7] is an odd parity bit.

The parity bit in the JEP106 identification code is not included.

For example, Arm Limited is assigned the code 0x7F 0x7F 0x7F 0x7F 0x3B.

The continuation code is the number of times 0x7F appears before the final number. For example, a component designed by Arm Limited has the code 0x4.
The identification code is bits[6:0] of the final number. For example, a component designed by Arm Limited has the code 0x3B.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Access Instructions

Accesses to this register use the following encodings:

Accessible at offset 0xFE8 from PMU

When FEAT_DoPD is implemented and !IsCorePowered(), accesses to this register generate an error response.
Otherwise, accesses to this register are RO.

()

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																								REVISION				JEDEC	DES_1

Configuration

Attributes

Field descriptions

Bits [31:8]:

REVISION, bits [7:4]:

JEDEC, bit [3]:

DES_1, bits [2:0]:

Access Instructions