Performance Monitors Peripheral Identification Register 1
Provides information to identify a Performance Monitor component.
For more information, see 'About the Peripheral identification scheme'.
This register is present only when FEAT_PMUv3_EXT is implemented and FEAT_PMU_PIDR is implemented. Otherwise, direct accesses to PMPIDR1 are RES0.
If FEAT_DoPD is implemented, this register is in the Core power domain. If FEAT_DoPD is not implemented, this register is in the Debug power domain.
PMPIDR1 is a 32-bit register.
This register is part of the PMU block.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | DES_0 | PART_1 | |||||||||||||||||||||||||||||
Reserved, RES0.
Designer, JEP106 identification code, bits [3:0].
The JEP106 identification and continuation codes are stored as follows:
These codes indicate the designer of the component and not the implementer, except where the two are the same. To obtain a number, or to see the assignment of these codes, contact JEDEC http://www.jedec.org.
A JEP106 identification and continuation code takes the following form:
The parity bit in the JEP106 identification code is not included.
For example, Arm Limited is assigned the code 0x7F 0x7F 0x7F 0x7F 0x3B.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Part number, which is selected by the designer of the component and stored as follows:
When a 12-bit part number is used, PMPIDR2.REVISION indicates revision information.
The choice of using a 12-bit part number or 16-bit part number is specific to the designer of the component.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Accesses to this register use the following encodings:
Accessible at offset 0xFE4 from PMU
()
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