TRCCONFIGR

External register TRCCONFIGR bits [31:0] are architecturally mapped to AArch64 System register TRCCONFIGR[31:0].

This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCCONFIGR are RES0.

Attributes

Field descriptions

Bits [31:19]:

ITO, bit [18] when TRCIDR0.ITE == '1':

Instrumentation Trace Override.

ITO	Meaning
0b0	Instrumentation Trace Override disabled.
0b1	Instrumentation Trace Override enabled.

This field is ignored when SelfHostedTraceEnabled() returns TRUE.

The reset behavior of this field is:

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bits [17:16]:

VMIDOPT, bit [15] when TRCIDR2.VMIDOPT == '01':

Virtual context identifier selection control.

VMIDOPT	Meaning
0b0	VTTBR_EL2.VMID is used as the Virtual context identifier.
0b1	CONTEXTIDR_EL2.PROCID is used as the Virtual context identifier.

when TRCIDR2.VMIDOPT == '00':

Reserved, RES0.

Virtual context identifier selection control.

VTTBR_EL2.VMID is used as the Virtual context identifier.

when TRCIDR2.VMIDOPT == '10':

Reserved, RES1.

Virtual context identifier selection control.

CONTEXTIDR_EL2.PROCID is used as the Virtual context identifier.

Otherwise:

QE, bits [14:13] when TRCIDR0.QSUPP == '01':

Q element generation control.

QE	Meaning
0b00	Q elements are disabled.
0b01	Q elements with instruction counts are enabled. Q elements without instruction counts are disabled.

Meaning

0b00

Q elements are disabled.

0b01

Q elements with instruction counts are enabled.

Q elements without instruction counts are disabled.

All other values are reserved.

when TRCIDR0.QSUPP == '10':

Q element generation control.

QE	Meaning
0b00	Q elements are disabled.
0b11	Q elements with instruction counts are enabled. Q elements without instruction counts are enabled.

Meaning

0b00

Q elements are disabled.

0b11

Q elements with instruction counts are enabled.

Q elements without instruction counts are enabled.

All other values are reserved.

when TRCIDR0.QSUPP == '11':

Q element generation control.

QE	Meaning
0b00	Q elements are disabled.
0b01	Q elements with instruction counts are enabled. Q elements without instruction counts are disabled.
0b11	Q elements with instruction counts are enabled. Q elements without instruction counts are enabled.

Meaning

0b00

Q elements are disabled.

0b01

Q elements with instruction counts are enabled.

Q elements without instruction counts are disabled.

0b11

Q elements with instruction counts are enabled.

Q elements without instruction counts are enabled.

All other values are reserved.

Otherwise:

RS, bit [12] when TRCIDR0.RETSTACK == '1':

Return stack control.

RS	Meaning
0b0	Return stack is disabled.
0b1	Return stack is enabled.

The reset behavior of this field is:

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

TS, bit [11] when TRCIDR0.TSSIZE != '00000':

Global timestamp tracing control.

TS	Meaning
0b0	Global timestamp tracing is disabled.
0b1	Global timestamp tracing is enabled.

The reset behavior of this field is:

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bits [10:8]:

VMID, bit [7] when TRCIDR2.VMIDSIZE != '00000':

Virtual context identifier tracing control.

VMID	Meaning
0b0	Virtual context identifier tracing is disabled.
0b1	Virtual context identifier tracing is enabled.

The reset behavior of this field is:

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

CID, bit [6] when TRCIDR2.CIDSIZE != '00000':

Context identifier tracing control.

CID	Meaning
0b0	Context identifier tracing is disabled.
0b1	Context identifier tracing is enabled.

The reset behavior of this field is:

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bit [5]:

CCI, bit [4] when TRCIDR0.TRCCCI == '1':

Cycle counting instruction tracing control.

CCI	Meaning
0b0	Cycle counting instruction tracing is disabled.
0b1	Cycle counting instruction tracing is enabled.

The reset behavior of this field is:

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

BB, bit [3] when TRCIDR0.TRCBB == '1':

Branch broadcasting control.

BB	Meaning
0b0	Branch broadcasting is disabled.
0b1	Branch broadcasting is enabled.

The reset behavior of this field is:

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bits [2:1]:

Bit [0]:

Accessing TRCCONFIGR

If the trace unit is not in the Idle state it is CONSTRAINED UNPREDICTABLE whether writes to this register are ignored.

Configuration

Attributes

Field descriptions

Bits [31:19]:

ITO, bit [18] when TRCIDR0.ITE == '1':

Otherwise:

Bits [17:16]:

VMIDOPT, bit [15] when TRCIDR2.VMIDOPT == '01':

when TRCIDR2.VMIDOPT == '00':

when TRCIDR2.VMIDOPT == '10':

Otherwise:

QE, bits [14:13] when TRCIDR0.QSUPP == '01':

when TRCIDR0.QSUPP == '10':

when TRCIDR0.QSUPP == '11':

Otherwise:

RS, bit [12] when TRCIDR0.RETSTACK == '1':

Otherwise:

TS, bit [11] when TRCIDR0.TSSIZE != '00000':

Otherwise:

Bits [10:8]:

VMID, bit [7] when TRCIDR2.VMIDSIZE != '00000':

Otherwise:

CID, bit [6] when TRCIDR2.CIDSIZE != '00000':

Otherwise:

Bit [5]:

CCI, bit [4] when TRCIDR0.TRCCCI == '1':

Otherwise:

BB, bit [3] when TRCIDR0.TRCBB == '1':

Otherwise:

Bits [2:1]:

Bit [0]:

Accessing TRCCONFIGR

TRCCONFIGR can be accessed through the external debug interface:

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0													ITO	RES0		VMIDOPT	QE		RS	TS	RES0			VMID	CID	RES0	CCI	BB	RES0		RES1