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TRCCONFIGR

Trace Configuration Register

Controls the tracing options.

Configuration

AArch64 System register TRCCONFIGR bits [31:0] are architecturally mapped to External register TRCCONFIGR[31:0].

This register is present only when FEAT_ETE is implemented and System register access to the trace unit registers is implemented. Otherwise, direct accesses to TRCCONFIGR are UNDEFINED.

Attributes

TRCCONFIGR is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0ITORES0VMIDOPTQERSTSRES0VMIDCIDRES0CCIBBRES0RES1

Bits [63:19]:

Reserved, RES0.

ITO, bit [18] when TRCIDR0.ITE == '1':

Instrumentation Trace Override.

ITOMeaning
0b0

Instrumentation Trace Override disabled.

0b1

Instrumentation Trace Override enabled.

This field is ignored when SelfHostedTraceEnabled() returns TRUE.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Bits [17:16]:

Reserved, RES0.

VMIDOPT, bit [15] when TRCIDR2.VMIDOPT == '01':

Virtual context identifier selection control.

VMIDOPTMeaning
0b0

VTTBR_EL2.VMID is used as the Virtual context identifier.

0b1

CONTEXTIDR_EL2.PROCID is used as the Virtual context identifier.

when TRCIDR2.VMIDOPT == '00':

Reserved, RES0.

Virtual context identifier selection control.

VTTBR_EL2.VMID is used as the Virtual context identifier.

when TRCIDR2.VMIDOPT == '10':

Reserved, RES1.

Virtual context identifier selection control.

CONTEXTIDR_EL2.PROCID is used as the Virtual context identifier.

Otherwise:

Reserved, RES0.

QE, bits [14:13] when TRCIDR0.QSUPP == '01':

Q element generation control.

QEMeaning
0b00

Q elements are disabled.

0b01

Q elements with instruction counts are enabled.

Q elements without instruction counts are disabled.

All other values are reserved.

when TRCIDR0.QSUPP == '10':

Q element generation control.

QEMeaning
0b00

Q elements are disabled.

0b11

Q elements with instruction counts are enabled.

Q elements without instruction counts are enabled.

All other values are reserved.

when TRCIDR0.QSUPP == '11':

Q element generation control.

QEMeaning
0b00

Q elements are disabled.

0b01

Q elements with instruction counts are enabled.

Q elements without instruction counts are disabled.

0b11

Q elements with instruction counts are enabled.

Q elements without instruction counts are enabled.

All other values are reserved.

Otherwise:

Reserved, RES0.

RS, bit [12] when TRCIDR0.RETSTACK == '1':

Return stack control.

RSMeaning
0b0

Return stack is disabled.

0b1

Return stack is enabled.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TS, bit [11] when TRCIDR0.TSSIZE != '00000':

Global timestamp tracing control.

TSMeaning
0b0

Global timestamp tracing is disabled.

0b1

Global timestamp tracing is enabled.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Bits [10:8]:

Reserved, RES0.

VMID, bit [7] when TRCIDR2.VMIDSIZE != '00000':

Virtual context identifier tracing control.

VMIDMeaning
0b0

Virtual context identifier tracing is disabled.

0b1

Virtual context identifier tracing is enabled.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

CID, bit [6] when TRCIDR2.CIDSIZE != '00000':

Context identifier tracing control.

CIDMeaning
0b0

Context identifier tracing is disabled.

0b1

Context identifier tracing is enabled.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Bit [5]:

Reserved, RES0.

CCI, bit [4] when TRCIDR0.TRCCCI == '1':

Cycle counting instruction tracing control.

CCIMeaning
0b0

Cycle counting instruction tracing is disabled.

0b1

Cycle counting instruction tracing is enabled.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

BB, bit [3] when TRCIDR0.TRCBB == '1':

Branch broadcasting control.

BBMeaning
0b0

Branch broadcasting is disabled.

0b1

Branch broadcasting is enabled.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Bits [2:1]:

Reserved, RES0.

Bit [0]:

Reserved, RES1.

Access Instructions

Must always be programmed.

TRCCONFIGR.QE must be set to 0b00 if TRCCONFIGR.BB is not 0.

If the trace unit is not in the Idle state it is CONSTRAINED UNPREDICTABLE whether writes to this register are ignored.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, TRCCONFIGR

(op0 = 0b10, op1 = 0b001, CRn = 0b0000, CRm = 0b0100, op2 = 0b000)

if !(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if CPACR_EL1().TTA == '1' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().TRC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCCONFIGR(); end; elsif PSTATE.EL == EL2 then if CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCCONFIGR(); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().TTA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCCONFIGR(); end; end;

MSR TRCCONFIGR, <Xt>

(op0 = 0b10, op1 = 0b001, CRn = 0b0000, CRm = 0b0100, op2 = 0b000)

if !(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if CPACR_EL1().TTA == '1' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().TRC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRCCONFIGR() = X{64}(t); end; elsif PSTATE.EL == EL2 then if CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRCCONFIGR() = X{64}(t); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().TTA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRCCONFIGR() = X{64}(t); end; end;

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