AMPIDR1

It is IMPLEMENTATION DEFINED whether AMPIDR1 is implemented in the Core power domain or in the Debug power domain.

This register is present only when FEAT_AMUv1 is implemented, FEAT_AMU_EXT is implemented, and FEAT_AMU_PIDR is implemented. Otherwise, direct accesses to AMPIDR1 are RES0.

Attributes

Field descriptions

Bits [31:8]:

DES_0, bits [7:4]:

Designer, JEP106 identification code, bits [3:0].

The JEP106 identification and continuation codes are stored as follows:

AMPIDR1.DES_0: JEP106 identification code bits[3:0].
AMPIDR2.DES_1: JEP106 identification code bits[6:4].
AMPIDR4.DES_2: JEP106 continuation code.

These codes indicate the designer of the component and not the implementer, except where the two are the same. To obtain a number, or to see the assignment of these codes, contact JEDEC http://www.jedec.org.

A JEP106 identification and continuation code takes the following form:

A sequence of zero or more numbers, all having the value 0x7F.
A following 8-bit number, that is not 0x7F, and where bit[7] is an odd parity bit.

The parity bit in the JEP106 identification code is not included.

For example, Arm Limited is assigned the code 0x7F 0x7F 0x7F 0x7F 0x3B.

The continuation code is the number of times 0x7F appears before the final number. For example, a component designed by Arm Limited has the code 0x4.
The identification code is bits[6:0] of the final number. For example, a component designed by Arm Limited has the code 0x3B.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

PART_1, bits [3:0]:

Part number, which is selected by the designer of the component and stored as follows:

For a component with a 12-bit part number:
- AMPIDR1.PART_1 contains part number bits [11:8].
- AMPIDR0.PART_0 contains part number bits [7:0].
For a component with a 16-bit part number:
- AMPIDR1.PART_1 contains part number bits [15:12].
- AMPIDR0.PART_0 contains part number bits [11:4].
- AMPIDR2.REVISION contains part number bits [3:0].

When a 12-bit part number is used, AMPIDR2.REVISION indicates revision information.

The choice of using a 12-bit part number or 16-bit part number is specific to the designer of the component.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Access Instructions

Accesses to this register use the following encodings:

Accessible at offset 0xFE4 from AMU

When ImpDefBool("AMU CoreSight management registers ignore access controls"), accesses to this register are RO.
When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Secure, and AMROOTCR().RA IN {'001', '000'}, accesses to this register are RAZ/WI.
When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Realm, and AMROOTCR().RA IN {'010', '000'}, accesses to this register are RAZ/WI.
When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMROOTCR().RA != '011', accesses to this register are RAZ/WI.
When FEAT_RME is not implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMSCR().NSRA == '0', accesses to this register are RAZ/WI.
Otherwise, accesses to this register are RO.

()