AMPIDR0 | Jon's Arm Reference

Provides information to identify an activity monitors component.

For more information, see 'About the Peripheral identification scheme'.

Configuration

It is IMPLEMENTATION DEFINED whether AMPIDR0 is implemented in the Core power domain or in the Debug power domain.

This register is present only when FEAT_AMUv1 is implemented, FEAT_AMU_EXT is implemented, and FEAT_AMU_PIDR is implemented. Otherwise, direct accesses to AMPIDR0 are RES0.

Attributes

Field descriptions

Bits [31:8]:

PART_0, bits [7:0]:

Part number, which is selected by the designer of the component and stored as follows:

For a component with a 12-bit part number:
- AMPIDR1.PART_1 contains part number bits [11:8].
- AMPIDR0.PART_0 contains part number bits [7:0].
For a component with a 16-bit part number:
- AMPIDR1.PART_1 contains part number bits [15:12].
- AMPIDR0.PART_0 contains part number bits [11:4].
- AMPIDR2.REVISION contains part number bits [3:0].

When a 12-bit part number is used, AMPIDR2.REVISION indicates revision information.

The choice of using a 12-bit part number or 16-bit part number is specific to the designer of the component.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Access Instructions

Accesses to this register use the following encodings:

Accessible at offset 0xFE0 from AMU

When ImpDefBool("AMU CoreSight management registers ignore access controls"), accesses to this register are RO.
When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Secure, and AMROOTCR().RA IN {'001', '000'}, accesses to this register are RAZ/WI.
When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Realm, and AMROOTCR().RA IN {'010', '000'}, accesses to this register are RAZ/WI.
When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMROOTCR().RA != '011', accesses to this register are RAZ/WI.
When FEAT_RME is not implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMSCR().NSRA == '0', accesses to this register are RAZ/WI.
Otherwise, accesses to this register are RO.

()

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																								PART_0