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TRFCR_EL2

Trace Filter Control Register (EL2)

Provides EL2 controls for Trace.

Configuration

AArch64 System register TRFCR_EL2 bits [31:0] are architecturally mapped to AArch32 System register HTRFCR[31:0].

This register is present only when FEAT_TRF is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to TRFCR_EL2 are UNDEFINED.

If EL2 is not implemented, this register is RES0 from EL3.

Attributes

TRFCR_EL2 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0DnVMKEEERES0TSRES0CXRES0E2TREE0HTRE

Bits [63:12]:

Reserved, RES0.

DnVM, bit [11] when FEAT_TRBEv1p1 is implemented:

Disable use of physical address trace buffer pointers.

DnVMMeaning
0b0

Use of physical address trace buffer pointers is permitted.

0b1

Use of physical address trace buffer pointers is disabled. The PE behaves as if TRBLIMITR_EL1.nVM is 0.

If EL2 is disabled in the owning Security state, or the trace buffer owning Exception level is EL2, then the Effective value of this field is 0.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

KE, bit [10] when FEAT_TRBE_EXC is implemented:

Kernel exception enable for TRBE Profiling exceptions taken to EL2.

KEMeaning
0b0

TRBE Profiling exceptions taken to EL2 are always masked at EL2.

0b1

Enabled TRBE Profiling exceptions taken to EL2 are masked at EL2 when PSTATE.PM is 1 and unmasked when PSTATE.PM is 0.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

EE, bits [9:8] when FEAT_TRBE_EXC is implemented:

Exception Enable.

EEMeaning
0b00

Disabled. TRBE Profiling exceptions for EL2 and EL1 are disabled. All of the following apply:

  • No trace buffer management events are recorded in TRBSR_EL2.
  • Unless enabled by a higher Exception level, TRBE Profiling exceptions are not generated.
  • TRBSR_EL1.IRQ drives the interrupt request signal TRBIRQ.
  • Accesses to TRBSR_EL1 at EL1 ignore the value of HCR_EL2.NV1 and accesses to TRBSR_EL1 at EL2 ignore the value of HCR_EL2.E2H.
0b01

Delegated. TRBE Profiling exceptions for EL2 are disabled, but might be enabled for EL1 by TRFCR_EL1.EE. All of the following apply:

  • No trace buffer management events are recorded in TRBSR_EL2.
  • TRBSR_EL2.IRQ is ignored and TRBE Profiling exceptions are not taken to EL2, other than for the case when the Effective value of HCR_EL2.TGE is 1.
0b10

Enabled. TRBE Profiling exceptions for EL2 are enabled for trace buffer management events targeting EL2, as follows:

  • Trace buffer management events due to a fault on a write to the trace buffer that would generate a Data Abort exception taken to EL2 if generated by a store instruction executed at the owning Exception level are recorded in TRBSR_EL2, unless they are configured to be recorded in TRBSR_EL3 by MDCR_EL3.TRBEE. If the trace buffer owning Exception level is EL2, then this means any fault on a write to the trace buffer. If the trace buffer owning Exception level is EL1, then this means any of the following faults on a write to the trace buffer:
    • Stage 2 faults.
    • If HCR_EL2.TEA is 1, synchronous External aborts.
    • If HCR_EL2.GPF is 1, Granule Protection Faults (GPFs).
  • Trace buffer management events due to Granule Protection Check faults other than GPFs on a write to the trace buffer are recorded in TRBSR_EL2, unless they are configured to be recorded in TRBSR_EL3 by MDCR_EL3.TRBEE.
  • TRBE Profiling exceptions are generated and taken to EL2 when unmasked and TRBSR_EL2.IRQ is 1.
0b11

Trap all. TRBE Profiling exceptions for EL2 are enabled for all trace buffer management events, as follows:

  • All trace buffer management events are recorded in TRBSR_EL2, unless they are configured to be recorded in TRBSR_EL3 by MDCR_EL3.TRBEE.
  • TRBE Profiling exceptions are generated and taken to EL2 when unmasked and TRBSR_EL2.IRQ is 1.

If the Effective value of MDCR_EL3.TRBEE is 0b00, then the Effective value of TRFCR_EL2.EE is 0b00. Otherwise, if EL2 is not implemented or the Effective value of SCR_EL3.{NS, EEL2} is {0, 0}, then the Effective value of TRFCR_EL2.EE is 0b01.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Bit [7]:

Reserved, RES0.

TS, bits [6:5]:

Timestamp Control. Controls which timebase is used for trace timestamps.

TSMeaningApplies when
0b00

Timestamp controlled by TRFCR_EL1.TS or TRFCR.TS.

0b01

Virtual timestamp. The traced timestamp is the physical counter value minus the value of CNTVOFF_EL2.

0b10

Guest physical timestamp. The traced timestamp is the physical counter value minus a physical offset. If any of the following are true, the physical offset is zero, otherwise the physical offset is the value of CNTPOFF_EL2:

When FEAT_ECV is implemented
0b11

Physical timestamp. The traced timestamp is the physical counter value.

If SelfHostedTraceEnabled() == FALSE, then this field is ignored by the PE.

The reset behavior of this field is:

Bit [4]:

Reserved, RES0.

CX, bit [3]:

CONTEXTIDR_EL2 and VMID trace enable.

CXMeaning
0b0

CONTEXTIDR_EL2 and VMID trace prohibited.

0b1

CONTEXTIDR_EL2 and VMID trace allowed.

If SelfHostedTraceEnabled() == FALSE, then this field is ignored by the PE.

The reset behavior of this field is:

Bit [2]:

Reserved, RES0.

E2TRE, bit [1]:

EL2 Trace Enable.

E2TREMeaning
0b0

Trace is prohibited at EL2.

0b1

Trace is allowed at EL2.

If SelfHostedTraceEnabled() == FALSE, then this field is ignored by the PE.

The reset behavior of this field is:

E0HTRE, bit [0]:

EL0 Trace Enable.

E0HTREMeaning
0b0

Trace is prohibited at EL0.

0b1

Trace is allowed at EL0.

If any of the following are true, then this field is ignored by the PE:

The reset behavior of this field is:

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, TRFCR_EL2

(op0 = 0b11, op1 = 0b100, CRn = 0b0001, CRm = 0b0010, op2 = 0b001)

if !(IsFeatureImplemented(FEAT_TRF) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && MDCR_EL3().TTRF == '1' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && MDCR_EL3().TTRF == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = TRFCR_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = TRFCR_EL2(); end;

MSR TRFCR_EL2, <Xt>

(op0 = 0b11, op1 = 0b100, CRn = 0b0001, CRm = 0b0010, op2 = 0b001)

if !(IsFeatureImplemented(FEAT_TRF) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && MDCR_EL3().TTRF == '1' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && MDCR_EL3().TTRF == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else TRFCR_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then TRFCR_EL2() = X{64}(t); end;

When FEAT_VHE is implemented:

MRS <Xt>, TRFCR_EL1

(op0 = 0b11, op1 = 0b000, CRn = 0b0001, CRm = 0b0010, op2 = 0b001)

if !(IsFeatureImplemented(FEAT_TRF) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && MDCR_EL3().TTRF == '1' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && MDCR_EL2().TTRF == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TTRF == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x880); else X{64}(t) = TRFCR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && MDCR_EL3().TTRF == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = TRFCR_EL2(); else X{64}(t) = TRFCR_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = TRFCR_EL1(); end;

When FEAT_VHE is implemented:

MSR TRFCR_EL1, <Xt>

(op0 = 0b11, op1 = 0b000, CRn = 0b0001, CRm = 0b0010, op2 = 0b001)

if !(IsFeatureImplemented(FEAT_TRF) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && MDCR_EL3().TTRF == '1' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().TRFCR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TTRF == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TTRF == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x880) = X{64}(t); else TRFCR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && MDCR_EL3().TTRF == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then TRFCR_EL2() = X{64}(t); else TRFCR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then TRFCR_EL1() = X{64}(t); end;

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