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TRCSSCCR<n>, n = 0 - 7

Trace Single-shot Comparator Control Register <n>

Controls the corresponding Single-shot Comparator Control resource.

Configuration

AArch64 System register TRCSSCCR<n> bits [31:0] are architecturally mapped to External register TRCSSCCR<n>[31:0].

This register is present only when FEAT_ETE is implemented and System register access to the trace unit registers is implemented. Otherwise, direct accesses to TRCSSCCR<n> are UNDEFINED.

Attributes

TRCSSCCR<n> is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0RSTARC[7]ARC[6]ARC[5]ARC[4]ARC[3]ARC[2]ARC[1]ARC[0]SAC[15]SAC[14]SAC[13]SAC[12]SAC[11]SAC[10]SAC[9]SAC[8]SAC[7]SAC[6]SAC[5]SAC[4]SAC[3]SAC[2]SAC[1]SAC[0]

Bits [63:25]:

Reserved, RES0.

RST, bit [24]:

Selects the Single-shot Comparator Control mode.

RSTMeaning
0b0

The Single-shot Comparator Control is in single-shot mode.

0b1

The Single-shot Comparator Control is in multi-shot mode.

The reset behavior of this field is:

ARC[<m>], bit [m+16], for m = 7 to 0:

Selects one or more Address Range Comparators for Single-shot control.

ARC[<m>]Meaning
0b0

The Address Range Comparator <m>, is not selected for Single-shot control.

0b1

The Address Range Comparator <m>, is selected for Single-shot control.

The reset behavior of this field is:

Accessing this field has the following behavior:

SAC[<m>], bit [m], for m = 15 to 0:

Selects one or more Single Address Comparators for Single-shot control.

SAC[<m>]Meaning
0b0

The Single Address Comparator <m>, is not selected for Single-shot control.

0b1

The Single Address Comparator <m>, is selected for Single-shot control.

The reset behavior of this field is:

Accessing this field has the following behavior:

Access Instructions

Must be programmed if any TRCRSCTLR<a>.GROUP == 0b0011 and TRCRSCTLR<a>.SINGLE_SHOT[n] == 1.

If the trace unit is not in the Idle state it is CONSTRAINED UNPREDICTABLE whether writes to this register are ignored.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, TRCSSCCR<m> ; Where m = 0-7

(op0 = 0b10, op1 = 0b001, CRn = 0b0001, CRm = 0b0:m[2:0], op2 = 0b010)

let m:integer = UInt(CRm[2:0]); if !(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)) then Undefined(); elsif m >= NUM_TRACE_SINGLE_SHOT_COMPARATOR_CONTROLS then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if CPACR_EL1().TTA == '1' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().TRC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCSSCCR(m); end; elsif PSTATE.EL == EL2 then if CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCSSCCR(m); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().TTA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCSSCCR(m); end; end;

MSR TRCSSCCR<m>, <Xt> ; Where m = 0-7

(op0 = 0b10, op1 = 0b001, CRn = 0b0001, CRm = 0b0:m[2:0], op2 = 0b010)

let m:integer = UInt(CRm[2:0]); if !(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)) then Undefined(); elsif m >= NUM_TRACE_SINGLE_SHOT_COMPARATOR_CONTROLS then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if CPACR_EL1().TTA == '1' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().TRC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRCSSCCR(m) = X{64}(t); end; elsif PSTATE.EL == EL2 then if CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRCSSCCR(m) = X{64}(t); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().TTA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRCSSCCR(m) = X{64}(t); end; end;

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