TRCRSCTLR<n> | Jon's Arm Reference

AArch64 System register TRCRSCTLR<n> bits [31:0] are architecturally mapped to External register TRCRSCTLR<n>[31:0].

This register is present only when FEAT_ETE is implemented and System register access to the trace unit registers is implemented. Otherwise, direct accesses to TRCRSCTLR<n> are UNDEFINED.

Resource selectors are implemented in pairs. Each odd numbered resource selector is part of a pair with the even numbered resource selector that is numbered as one less than it. For example, resource selectors 2 and 3 form a pair.

Attributes

Field descriptions

Bits [63:22]:

PAIRINV, bit [21] when n is even:

Controls whether the combined result from a resource selector pair is inverted.

PAIRINV	Meaning
0b0	Do not invert the combined output of the 2 resource selectors.
0b1	Invert the combined output of the 2 resource selectors.

If:

A is the register TRCRSCTLR<n>.
B is the register TRCRSCTLR<n+1>.

Then the combined output of the 2 resource selectors A and B depends on the value of (A.PAIRINV, A.INV, B.INV) as follows:

0b000 -> A and B.
0b001 -> Reserved.
0b010 -> not(A) and B.
0b011 -> not(A) and not(B).
0b100 -> not(A) or not(B).
0b101 -> not(A) or B.
0b110 -> Reserved.
0b111 -> A or B.

The reset behavior of this field is:

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

INV, bit [20]:

Controls whether the resource, that TRCRSCTLR<n>.GROUP and TRCRSCTLR<n>.SELECT selects, is inverted.

INV	Meaning
0b0	Do not invert the output of this selector.
0b1	Invert the output of this selector.

The reset behavior of this field is:

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

GROUP, bits [19:16]:

Selects a group of resources.

GROUP	Meaning	SELECT
0b0000	External Input Selectors.	SELECT encoding for External Input Selectors
0b0001	PE Comparator Inputs.	SELECT encoding for PE Comparator Inputs
0b0010	Counters and Sequencer.	SELECT encoding for Counters and Sequencer
0b0011	Single-shot Comparator Controls.	SELECT encoding for Single-shot Comparator Controls
0b0100	Single Address Comparators.	SELECT encoding for Single Address Comparators
0b0101	Address Range Comparators.	SELECT encoding for Address Range Comparators
0b0110	Context Identifier Comparators.	SELECT encoding for Context Identifier Comparators
0b0111	Virtual Context Identifier Comparators.	SELECT encoding for Virtual Context Identifier Comparators

All other values are reserved.

The reset behavior of this field is:

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

SELECT, bits [15:0]:

Resource Specific Controls. Contains the controls specific to the resource group selected by GROUP, described in the following sections.

SELECT encoding for External Input Selectors

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0												EXTIN[3]	EXTIN[2]	EXTIN[1]	EXTIN[0]

Bits [15:4]:

Reserved, RES0.

EXTIN[<m>], bit [m], for m = 3 to 0:

Selects one or more External Inputs.

EXTIN[<m>]	Meaning
0b0	Ignore EXTIN <m>.
0b1	Select EXTIN <m>.

This bit is RES0 if m >= TRCIDR5.NUMEXTINSEL.

The reset behavior of this field is:

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

SELECT encoding for PE Comparator Inputs

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0								PECOMP[7]	PECOMP[6]	PECOMP[5]	PECOMP[4]	PECOMP[3]	PECOMP[2]	PECOMP[1]	PECOMP[0]

Bits [15:8]:

Reserved, RES0.

PECOMP[<m>], bit [m], for m = 7 to 0:

Selects one or more PE Comparator Inputs.

PECOMP[<m>]	Meaning
0b0	Ignore PE Comparator Input <m>.
0b1	Select PE Comparator Input <m>.

This bit is RES0 if m >= TRCIDR4.NUMPC.

The reset behavior of this field is:

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

SELECT encoding for Counters and Sequencer

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0								SEQUENCER[3]	SEQUENCER[2]	SEQUENCER[1]	SEQUENCER[0]	COUNTERS[3]	COUNTERS[2]	COUNTERS[1]	COUNTERS[0]

Bits [15:8]:

Reserved, RES0.

SEQUENCER[<m>], bit [m+4], for m = 3 to 0:

Sequencer states.

SEQUENCER[<m>]	Meaning
0b0	Ignore Sequencer state <m>.
0b1	Select Sequencer state <m>.

This bit is RES0 if m >= TRCIDR5.NUMSEQSTATE.

The reset behavior of this field is:

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

COUNTERS[<m>], bit [m], for m = 3 to 0:

Counters resources at zero.

COUNTERS[<m>]	Meaning
0b0	Ignore Counter <m>.
0b1	Select Counter <m> is zero.

This bit is RES0 if m >= TRCIDR5.NUMCNTR.

The reset behavior of this field is:

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

SELECT encoding for Single-shot Comparator Controls

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0								SINGLE_SHOT[7]	SINGLE_SHOT[6]	SINGLE_SHOT[5]	SINGLE_SHOT[4]	SINGLE_SHOT[3]	SINGLE_SHOT[2]	SINGLE_SHOT[1]	SINGLE_SHOT[0]

Bits [15:8]:

Reserved, RES0.

SINGLE_SHOT[<m>], bit [m], for m = 7 to 0:

Selects one or more Single-shot Comparator Controls.

SINGLE_SHOT[<m>]	Meaning
0b0	Ignore Single-shot Comparator Control <m>.
0b1	Select Single-shot Comparator Control <m>.

This bit is RES0 if m >= TRCIDR4.NUMSSCC.

The reset behavior of this field is:

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

SELECT encoding for Single Address Comparators

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SAC[15]	SAC[14]	SAC[13]	SAC[12]	SAC[11]	SAC[10]	SAC[9]	SAC[8]	SAC[7]	SAC[6]	SAC[5]	SAC[4]	SAC[3]	SAC[2]	SAC[1]	SAC[0]

SAC[<m>], bit [m], for m = 15 to 0:

Selects one or more Single Address Comparators.

SAC[<m>]	Meaning
0b0	Ignore Single Address Comparator <m>.
0b1	Select Single Address Comparator <m>.

This bit is RES0 if m >= 2 × TRCIDR4.NUMACPAIRS.

The reset behavior of this field is:

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

SELECT encoding for Address Range Comparators

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0								ARC[7]	ARC[6]	ARC[5]	ARC[4]	ARC[3]	ARC[2]	ARC[1]	ARC[0]

Bits [15:8]:

Reserved, RES0.

ARC[<m>], bit [m], for m = 7 to 0:

Selects one or more Address Range Comparators.

ARC[<m>]	Meaning
0b0	Ignore Address Range Comparator <m>.
0b1	Select Address Range Comparator <m>.

This bit is RES0 if m >= TRCIDR4.NUMACPAIRS.

The reset behavior of this field is:

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

SELECT encoding for Context Identifier Comparators

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0								CID[7]	CID[6]	CID[5]	CID[4]	CID[3]	CID[2]	CID[1]	CID[0]

Bits [15:8]:

Reserved, RES0.

CID[<m>], bit [m], for m = 7 to 0:

Selects one or more Context Identifier Comparators.

CID[<m>]	Meaning
0b0	Ignore Context Identifier Comparator <m>.
0b1	Select Context Identifier Comparator <m>.

This bit is RES0 if m >= TRCIDR4.NUMCIDC.

The reset behavior of this field is:

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

SELECT encoding for Virtual Context Identifier Comparators

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0								VMID[7]	VMID[6]	VMID[5]	VMID[4]	VMID[3]	VMID[2]	VMID[1]	VMID[0]

Bits [15:8]:

Reserved, RES0.

VMID[<m>], bit [m], for m = 7 to 0:

Selects one or more Virtual Context Identifier Comparators.

VMID[<m>]	Meaning
0b0	Ignore Virtual Context Identifier Comparator <m>.
0b1	Select Virtual Context Identifier Comparator <m>.

This bit is RES0 if m >= TRCIDR4.NUMVMIDC.

The reset behavior of this field is:

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

Access Instructions

Must be programmed if any of the following are true:

TRCCNTCTLR<a>.RLDEVENT_TYPE == 0 and TRCCNTCTLR<a>.RLDEVENT_SEL == n.
TRCCNTCTLR<a>.RLDEVENT_TYPE == 1 and TRCCNTCTLR<a>.RLDEVENT_SEL == n/2.
TRCCNTCTLR<a>.CNTEVENT_TYPE == 0 and TRCCNTCTLR<a>.CNTEVENT_SEL == n.
TRCCNTCTLR<a>.CNTEVENT_TYPE == 1 and TRCCNTCTLR<a>.CNTEVENT_SEL == n/2.
TRCEVENTCTL0R.EVENT0_TYPE == 0 and TRCEVENTCTL0R.EVENT0_SEL == n.
TRCEVENTCTL0R.EVENT0_TYPE == 1 and TRCEVENTCTL0R.EVENT0_SEL == n/2.
TRCEVENTCTL0R.EVENT1_TYPE == 0 and TRCEVENTCTL0R.EVENT1_SEL == n.
TRCEVENTCTL0R.EVENT1_TYPE == 1 and TRCEVENTCTL0R.EVENT1_SEL == n/2.
TRCEVENTCTL0R.EVENT2_TYPE == 0 and TRCEVENTCTL0R.EVENT2_SEL == n.
TRCEVENTCTL0R.EVENT2_TYPE == 1 and TRCEVENTCTL0R.EVENT2_SEL == n/2.
TRCEVENTCTL0R.EVENT3_TYPE == 0 and TRCEVENTCTL0R.EVENT3_SEL == n.
TRCEVENTCTL0R.EVENT3_TYPE == 1 and TRCEVENTCTL0R.EVENT3_SEL == n/2.
TRCSEQEVR<a>.B_TYPE == 0 and TRCSEQEVR<a>.B_SEL = n.
TRCSEQEVR<a>.B_TYPE == 1 and TRCSEQEVR<a>.B_SEL = n/2.
TRCSEQEVR<a>.F_TYPE == 0 and TRCSEQEVR<a>.F_SEL = n.
TRCSEQEVR<a>.F_TYPE == 1 and TRCSEQEVR<a>.F_SEL = n/2.
TRCSEQRSTEVR.RST_TYPE == 0 and TRCSEQRSTEVR.RST_SEL == n.
TRCSEQRSTEVR.RST_TYPE == 1 and TRCSEQRSTEVR.RST_SEL == n/2.
TRCTSCTLR.EVENT_TYPE == 0 and TRCTSCTLR.EVENT_SEL == n.
TRCTSCTLR.EVENT_TYPE == 1 and TRCTSCTLR.EVENT_SEL == n/2.
TRCVICTLR.EVENT_TYPE == 0 and TRCVICTLR.EVENT_SEL == n.
TRCVICTLR.EVENT_TYPE == 1 and TRCVICTLR.EVENT_SEL == n/2.

If the trace unit is not in the Idle state it is CONSTRAINED UNPREDICTABLE whether writes to this register are ignored.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, TRCRSCTLR<m> ; Where m = 2-31

(op0 = 0b10, op1 = 0b001, CRn = 0b0001, CRm = m[3:0], op2 = 0b00:m[4])

let m:integer = UInt(op2[0] :: CRm[3:0]); if !(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)) then Undefined(); elsif m >= NUM_TRACE_RESOURCE_SELECTOR_PAIRS * 2 then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if CPACR_EL1().TTA == '1' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().TRC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCRSCTLR(m); end; elsif PSTATE.EL == EL2 then if CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCRSCTLR(m); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().TTA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCRSCTLR(m); end; end;

MSR TRCRSCTLR<m>, <Xt> ; Where m = 2-31

(op0 = 0b10, op1 = 0b001, CRn = 0b0001, CRm = m[3:0], op2 = 0b00:m[4])

let m:integer = UInt(op2[0] :: CRm[3:0]); if !(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)) then Undefined(); elsif m >= NUM_TRACE_RESOURCE_SELECTOR_PAIRS * 2 then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if CPACR_EL1().TTA == '1' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().TRC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRCRSCTLR(m) = X{64}(t); end; elsif PSTATE.EL == EL2 then if CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRCRSCTLR(m) = X{64}(t); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().TTA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRCRSCTLR(m) = X{64}(t); end; end;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0										PAIRINV	INV	GROUP				SELECT

TRCRSCTLR<n>, n = 2 - 31

Configuration

Attributes

Field descriptions

Bits [63:22]:

PAIRINV, bit [21] when n is even:

Otherwise:

INV, bit [20]:

GROUP, bits [19:16]:

SELECT, bits [15:0]:

SELECT encoding for External Input Selectors

Bits [15:4]:

EXTIN[<m>], bit [m], for m = 3 to 0:

SELECT encoding for PE Comparator Inputs

Bits [15:8]:

PECOMP[<m>], bit [m], for m = 7 to 0:

SELECT encoding for Counters and Sequencer

Bits [15:8]:

SEQUENCER[<m>], bit [m+4], for m = 3 to 0:

COUNTERS[<m>], bit [m], for m = 3 to 0:

SELECT encoding for Single-shot Comparator Controls

Bits [15:8]:

SINGLE_SHOT[<m>], bit [m], for m = 7 to 0:

SELECT encoding for Single Address Comparators

SAC[<m>], bit [m], for m = 15 to 0:

SELECT encoding for Address Range Comparators

Bits [15:8]:

ARC[<m>], bit [m], for m = 7 to 0:

SELECT encoding for Context Identifier Comparators

Bits [15:8]:

CID[<m>], bit [m], for m = 7 to 0:

SELECT encoding for Virtual Context Identifier Comparators

Bits [15:8]:

VMID[<m>], bit [m], for m = 7 to 0:

Access Instructions