Trace Buffer ID Register
Describes constraints on using the Trace Buffer Unit to software, including whether the Trace Buffer Unit can be programmed at the current Exception level.
AArch64 System register TRBIDR_EL1 bits [63:0] are architecturally mapped to External register TRBIDR_EL1[63:0] when FEAT_TRBE_EXT is implemented.
This register is present only when FEAT_TRBE is implemented. Otherwise, direct accesses to TRBIDR_EL1 are UNDEFINED.
TRBIDR_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | MaxBuffSize | ||||||||||||||||||||||||||||||
| RES0 | MPAM2 | MPAM | EA | AddrMode | F | P | Align | ||||||||||||||||||||||||
Reserved, RES0.
Maximum supported trace buffer size. Reserved for software use.
The only permitted value is 0x0000, indicating there is no limit to the maximum buffer size.
Permitted values relate to the values an implementation is permitted to set this field to. A hypervisor might trap accesses to this register and use other values to describe limitations of its virtualization support to a guest operating system, as follows:
The maximum buffer size, in bytes, is expressed using the following function:
if IsZero(E), then UInt(M:Zeros(12)) else UInt('1':M:Zeros(UInt(E)+11))
For example:
Reads as 0x0000.
Access to this field is RO.
Reserved, RES0.
FEAT_MPAMv2 extensions. Indicates Memory Partitioning and Monitoring (MPAM) support using FEAT_MPAMv2 in the Trace Buffer Unit when using External mode.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| MPAM2 | Meaning |
|---|---|
| 0b0000 |
FEAT_MPAMv2 is not implemented by the PE. |
| 0b0001 |
FEAT_MPAMv2 is implemented by the Trace Buffer Unit, using Default physical PARTID and PMG values in External mode. |
| 0b0010 |
Trace Buffer MPAM extensions implemented, using FEAT_MPAMv2. |
When FEAT_MPAMv2 is not implemented by the PE, the only permitted value is 0b0000.
When FEAT_MPAMv2 is implemented by the PE, the value 0b0000 is not permitted.
FEAT_TRBE_MPAM implements the functionality identified by the value 0b0010.
Access to this field is RO.
Reserved, RES0.
FEAT_MPAMv0p1 or FEAT_MPAMv1p0 extensions. Indicates Memory Partitioning and Monitoring (MPAM) support using FEAT_MPAMv0p1 or FEAT_MPAMv1p0 in the Trace Buffer Unit when using External mode.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| MPAM | Meaning |
|---|---|
| 0b0000 |
FEAT_MPAMv0p1 and FEAT_MPAMv1p0 are not implemented by the PE. |
| 0b0001 |
FEAT_MPAMv0p1 or FEAT_MPAMv1p0 is implemented by the Trace Buffer Unit, using Default physical PARTID and PMG values in External mode. |
| 0b0010 |
Trace Buffer MPAM extensions implemented, using FEAT_MPAMv0p1 or FEAT_MPAMv1p0. |
When FEAT_MPAMv0p1 and FEAT_MPAMv1p0 are not implemented by the PE, the only permitted value is 0b0000.
When either FEAT_MPAMv0p1 or FEAT_MPAMv1p0 is implemented by the PE, the value 0b0000 is not permitted.
FEAT_TRBE_MPAM implements the functionality identified by the value 0b0010.
Access to this field is RO.
Reserved, RES0.
External Abort handling. Describes how the PE manages External aborts on writes made by the Trace Buffer Unit to the trace buffer.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| EA | Meaning |
|---|---|
| 0b0000 |
Not described. |
| 0b0001 |
The PE ignores External aborts on writes made by the Trace Buffer Unit. |
| 0b0010 |
An External abort on a write made by the Trace Buffer Unit generates an asynchronous SError exception at the PE. |
All other values are reserved.
From Armv9.3, the value 0b0000 is not permitted.
The behavior described by this field does not apply for External aborts on a translation table walk, translation table update, or GPT walk made by the Trace Buffer Unit that are reported as MMU faults using TRBSR_ELx. For more information, see 'External aborts'.
Access to this field is RO.
Address Modes. Describes the addressing modes available for the trace buffer.
| AddrMode | Meaning |
|---|---|
| 0b00 |
Virtual and physical address modes are supported. |
| 0b01 |
Only virtual address mode is supported. |
| 0b10 |
Reserved for software use under virtualization, to show that only physical address mode is supported. |
Other values are reserved.
If the Effective value of TRFCR_EL2.DnVM is 1 and the value returned for TRBIDR_EL1.P is 0, then this field reads as 0b01. Otherwise, this field reads as 0b00.
A hypervisor might trap accesses to this register to describe limitations of its virtualization support to a guest operating system.
Flag updates. Describes how address translations performed by the Trace Buffer Unit manage the Access flag and dirty state.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| F | Meaning |
|---|---|
| 0b0 |
Hardware management of the Access flag and dirty state for accesses made by the Trace Buffer Unit is always disabled for all translation stages. |
| 0b1 |
Hardware management of the Access flag and dirty state for accesses made by the Trace Buffer Unit is controlled in the same way as explicit memory accesses in the trace buffer owning translation regime. |
If hardware management of the Access flag is disabled for a stage of translation, an access to a Page or Block with the Access flag bit not set in the descriptor will generate an Access Flag fault.
If hardware management of the dirty state is disabled for a stage of translation, an access to a Page or Block will ignore the Dirty Bit Modifier in the descriptor and might generate a Permission fault, depending on the values of the access permission bits in the descriptor.
From Armv9.3, the value 0 is not permitted.
Access to this field is RO.
Programming not allowed. When read at EL3, this field reads as zero. Otherwise, indicates that the trace buffer owning Exception level is a higher Exception level or the trace buffer owning Security state is not the current Security state.
| P | Meaning |
|---|---|
| 0b0 |
Programming is allowed. |
| 0b1 |
Programming not allowed. |
The value read from this field depends on the current Exception level and the Effective values of MDCR_EL3.NSTB, MDCR_EL3.NSTBE, and MDCR_EL2.E2TB:
If EL3 is implemented and MDCR_EL3.{NSTB, NSTBE} has a reserved combination of values, then this field reads as an UNKNOWN value from EL2 and EL1.
If EL2 is implemented and enabled in the current Security state, and MDCR_EL2.E2TB has a reserved value, then this field reads as an UNKNOWN value from EL1.
Otherwise, this field reads as zero.
Defines the minimum alignment constraint for writes to TRBPTR_EL1 and TRBTRG_EL1.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| Align | Meaning |
|---|---|
| 0b0000 |
Byte. |
| 0b0001 |
Halfword. |
| 0b0010 |
Word. |
| 0b0011 |
Doubleword. |
| 0b0100 |
16 bytes. |
| 0b0101 |
32 bytes. |
| 0b0110 |
64 bytes. |
| 0b0111 |
128 bytes. |
| 0b1000 |
256 bytes. |
| 0b1001 |
512 bytes. |
| 0b1010 |
1KB. |
| 0b1011 |
2KB. |
All other values are reserved.
Access to this field is RO.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, TRBIDR_EL1
(op0 = 0b11, op1 = 0b000, CRn = 0b1001, CRm = 0b1011, op2 = 0b111)
if !IsFeatureImplemented(FEAT_TRBE) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().TRBIDR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRBIDR_EL1(); end; elsif PSTATE.EL == EL2 then if IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRBIDR_EL1(); end; elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRBIDR_EL1(); end; end;
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