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SCTLR2_EL1

System Control Register (EL1)

Provides top-level control of the system, including its memory system, at EL1 and EL0.

Configuration

This register is present only when FEAT_SCTLR2 is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to SCTLR2_EL1 are UNDEFINED.

Attributes

SCTLR2_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0TLBOSNISFDITBTDBTD0EnIA2EnIB2EnDA2EnDB2RES0CPTM0CPTMCPTA0CPTAEnPACM0EnPACMEnIDCP128EASEEnANERREnADERRNMEARES0

Bits [63:27]:

Reserved, RES0.

TLBOSNIS, bit [26] when FEAT_TLBID is implemented:

TLBI for Outer shareable excludes Inner shareable.

This control applies to TLBI OS instructions executed at EL1.

TLBOSNISMeaning
0b0

TLBI OS instructions affect TLBs in the Inner and Outer shareability domains.

0b1

TLBI OS instructions affect TLBs in the Outer shareability domain, but not in the Inner shareability domain.

This field is ignored by the PE and treated as zero when any of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

FDIT, bit [25] when FEAT_FDIT is implemented:

Enforce data-independent timing for execution at EL0.

FDITMeaning
0b0

This control does not affect data-independent timing of execution.

0b1

Data-independent timing of execution is enforced.

When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on execution.

This field is ignored by the PE and treated as zero when any of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

BTD, bit [24] when FEAT_PAuth_EnhCtl is implemented:

Controls the implicit BTI behavior of the following instructions at EL1:

BTDMeaning
0b0

The implicit BTI behavior of the instructions is unaffected.

0b1

When the instructions are executed, they have no implicit BTI behavior.

This field is ignored by the PE and treated as zero when any of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

BTD0, bit [23] when FEAT_PAuth_EnhCtl is implemented:

Controls the implicit BTI behavior of the following instructions at EL0 in the EL1&0 translation regime:

BTD0Meaning
0b0

The implicit BTI behavior of the instructions is unaffected.

0b1

When the instructions are executed, they have no implicit BTI behavior.

This field is ignored by the PE and treated as zero when any of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

EnIA2, bit [22] when FEAT_PAuth_EnhCtl is implemented:

Controls enabling of pointer authentication of instruction addresses using the APIAKey_EL1 key, at EL0 in the EL1&0 translation regime. This field is used in conjunction with SCTLR_EL1.EnIA as follows:

EnIA2EnIABehavior at EL0
0b00b0Disabled
0b00b1Enabled
0b10b0Enabled
0b10b1Disabled

This field is ignored by the PE and treated as zero when any of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

EnIB2, bit [21] when FEAT_PAuth_EnhCtl is implemented:

Controls enabling of pointer authentication of instruction addresses using the APIBKey_EL1 key, at EL0 in the EL1&0 translation regime. This field is used in conjunction with SCTLR_EL1.EnIB as follows:

EnIB2EnIBBehavior at EL0
0b00b0Disabled
0b00b1Enabled
0b10b0Enabled
0b10b1Disabled

This field is ignored by the PE and treated as zero when any of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

EnDA2, bit [20] when FEAT_PAuth_EnhCtl is implemented:

Controls enabling of pointer authentication of data addresses using the APDAKey_EL1 key, at EL0 in the EL1&0 translation regime. This field is used in conjunction with SCTLR_EL1.EnDA as follows:

EnDA2EnDABehavior at EL0
0b00b0Disabled
0b00b1Enabled
0b10b0Enabled
0b10b1Disabled

This field is ignored by the PE and treated as zero when any of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

EnDB2, bit [19] when FEAT_PAuth_EnhCtl is implemented:

Controls enabling of pointer authentication of data addresses using the APDBKey_EL1 key, at EL0 in the EL1&0 translation regime. This field is used in conjunction with SCTLR_EL1.EnDB as follows:

EnDB2EnDBBehavior at EL0
0b00b0Disabled
0b00b1Enabled
0b10b0Enabled
0b10b1Disabled

This field is ignored by the PE and treated as zero when any of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

Bits [18:13]:

Reserved, RES0.

CPTM0, bit [12] when FEAT_CPA2 is implemented:

This field controls unprivileged Checked Pointer Arithmetic for Multiplication.

CPTM0Meaning
0b0

Pointer Arithmetic for Multiplication is not checked.

0b1

Pointer Arithmetic for Multiplication is checked.

When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on execution.

This field is ignored by the PE and treated as zero when any of the following are true:

If the Effective value of SCTLR2_EL1.CPTA0 is 0, then the Effective value of this field is 0.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

CPTM, bit [11] when FEAT_CPA2 is implemented:

This field controls Checked Pointer Arithmetic for Multiplication at EL1.

CPTMMeaning
0b0

Pointer Arithmetic for Multiplication is not checked.

0b1

Pointer Arithmetic for Multiplication is checked.

This field is ignored by the PE and treated as zero when any of the following are true:

If the Effective value of SCTLR2_EL1.CPTA is 0, then the Effective value of this field is 0.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

CPTA0, bit [10] when FEAT_CPA2 is implemented:

This field controls unprivileged Checked Pointer Arithmetic for Addition.

CPTA0Meaning
0b0

Pointer Arithmetic for Addition is not checked.

0b1

Pointer Arithmetic for Addition is checked.

When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on execution.

This field is ignored by the PE and treated as zero when any of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

CPTA, bit [9] when FEAT_CPA2 is implemented:

This field controls Checked Pointer Arithmetic for Addition at EL1.

CPTAMeaning
0b0

Pointer Arithmetic for Addition is not checked.

0b1

Pointer Arithmetic for Addition is checked.

This field is ignored by the PE and treated as zero when any of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

EnPACM0, bit [8] when FEAT_PAuth_LR is implemented:

PACM Enable at EL0. Controls the effect of a PACM instruction at EL0.

EnPACM0Meaning
0b0

The effects of PACM are disabled at EL0.

0b1

A PACM instruction at EL0 causes PSTATE.PACM to be set to 1.

When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on execution at EL0.

This field is ignored by the PE and treated as zero when any of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

EnPACM, bit [7] when FEAT_PAuth_LR is implemented:

PACM Enable at EL1. Controls the effect of a PACM instruction at EL1.

EnPACMMeaning
0b0

The effects of PACM are disabled at EL1.

0b1

A PACM instruction at EL1 causes PSTATE.PACM to be set to 1.

This field is ignored by the PE and treated as zero when any of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

EnIDCP128, bit [6] when FEAT_SYSREG128 is implemented:

Enables access to IMPLEMENTATION DEFINED 128-bit System registers.

EnIDCP128Meaning
0b0

Accesses at EL0 to IMPLEMENTATION DEFINED 128-bit System registers are trapped to EL1 using an ESR_EL1.EC value of 0x14, unless the access generates a higher priority exception.

Disables the functionality of the 128-bit IMPLEMENTATION DEFINED System registers that are accessible at EL1.

0b1

No accesses are trapped by this control.

This field is ignored by the PE and treated as zero when any of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

EASE, bit [5] when FEAT_DoubleFault2 is implemented:

External Aborts to SError exception vector.

EASEMeaning
0b0

Synchronous External abort exceptions taken to EL1 are taken to the appropriate synchronous exception vector offset from VBAR_EL1.

0b1

Synchronous External abort exceptions taken to EL1 are taken to the appropriate SError exception vector offset from VBAR_EL1.

This field is ignored by the PE and treated as zero when any of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

EnANERR, bit [4] when FEAT_ANERR is implemented:

Enable Asynchronous Normal Read Error.

EnANERRMeaning
0b0

External aborts on Normal memory reads generate synchronous Data Abort exceptions in the EL1&0 translation regime.

0b1

External aborts on Normal memory reads generate synchronous Data Abort or asynchronous SError exceptions in the EL1&0 translation regime.

Implementation-specific exceptions to applications of this field are described in 'Taking error exceptions'.

Setting this field to 0 does not guarantee that the PE is able to take a synchronous Data Abort exception for an External abort on a Normal memory read in every case. There might be implementation-specific circumstances when an error on a load cannot be taken synchronously. These circumstances should be rare enough that treating such occurrences as fatal does not cause a significant increase in failure rate.

If FEAT_SVE is implemented, SCTLR2_EL1.EnANERR is 0, and the access generating the External abort is due to any Active element of an SVE Non-fault vector load instruction or an Active element that is not the First active element of an SVE First-fault vector load instruction, then no exception is generated and the External abort is reported in the FFR.

Setting this field to 0 might have a performance impact for Normal memory reads.

This field is ignored by the PE and treated as zero when any of the following are true:

Otherwise, this field is ignored by the PE and treated as one when all of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

EnADERR, bit [3] when FEAT_ADERR is implemented:

Enable Asynchronous Device Read Error.

EnADERRMeaning
0b0

External aborts on Device memory reads generate synchronous Data Abort exceptions in the EL1&0 translation regime.

0b1

External aborts on Device memory reads generate synchronous Data Abort or asynchronous SError exceptions in the EL1&0 translation regime.

Implementation-specific exceptions to applications of this field are described in 'Taking error exceptions'.

Setting this field to 0 does not guarantee that the PE is able to take a synchronous Data Abort exception for an External abort on a Device memory read in every case. There might be implementation-specific circumstances when an error on a load cannot be taken synchronously. These circumstances should be rare enough that treating such occurrences as fatal does not cause a significant increase in failure rate.

If FEAT_SVE is implemented, SCTLR2_EL1.EnADERR is 0, and the access generating the External abort is due to any Active element of an SVE Non-fault vector load instruction or an Active element that is not the First active element of an SVE First-fault vector load instruction, then no exception is generated and the External abort is reported in the FFR.

Setting this field to 0 might have a performance impact for Device memory reads.

This field is ignored by the PE and treated as zero when any of the following are true:

Otherwise, this field is ignored by the PE and treated as one when all of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

NMEA, bit [2] when FEAT_DoubleFault2 is implemented:

Non-maskable External Aborts. Controls whether PSTATE.A masks physical SError exceptions at EL1.

NMEAMeaning
0b0

Physical SError exceptions are not taken at EL1 if PSTATE.A == 1, unless routed to a higher Exception level.

0b1

Physical SError exceptions are taken at EL1 regardless of the value of PSTATE.A, unless routed to a higher Exception level.

This field has no effect on the masking of virtual and delegated SError interrupts.

This field is ignored by the PE and treated as zero when any of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

Bits [1:0]:

Reserved, RES0.

Access Instructions

When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name SCTLR2_EL1 or SCTLR2_EL12 are not guaranteed to be ordered with respect to accesses using the other accessor name.

If FEAT_SRMASK is implemented, accesses to SCTLR2_EL1 are masked by SCTLR2MASK_EL1.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, SCTLR2_EL1

(op0 = 0b11, op1 = 0b000, CRn = 0b0001, CRm = 0b0000, op2 = 0b011)

if !(IsFeatureImplemented(FEAT_SCTLR2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && SCR_EL3().SCTLR2En == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().TRVM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().SCTLR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().SCTLR2En == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().SCTLR2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x278); else X{64}(t) = SCTLR2_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().SCTLR2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = SCTLR2_EL2(); else X{64}(t) = SCTLR2_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = SCTLR2_EL1(); end;

MSR SCTLR2_EL1, <Xt>

(op0 = 0b11, op1 = 0b000, CRn = 0b0001, CRm = 0b0000, op2 = 0b011)

if !(IsFeatureImplemented(FEAT_SCTLR2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && SCR_EL3().SCTLR2En == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().TVM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGWTR_EL2().SCTLR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().SCTLR2En == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().SCTLR2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x278) = X{64}(t); else SCTLR2_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().SCTLR2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then SCTLR2_EL2() = X{64}(t); else SCTLR2_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then SCTLR2_EL1() = X{64}(t); end;

When FEAT_VHE is implemented:

MRS <Xt>, SCTLR2_EL12

(op0 = 0b11, op1 = 0b101, CRn = 0b0001, CRm = 0b0000, op2 = 0b011)

if !(IsFeatureImplemented(FEAT_SCTLR2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR_EL3().SCTLR2En == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then X{64}(t) = NVMem(0x278); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && SCR_EL3().SCTLR2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = SCTLR2_EL1(); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X{64}(t) = SCTLR2_EL1(); else Undefined(); end; end;

When FEAT_VHE is implemented:

MSR SCTLR2_EL12, <Xt>

(op0 = 0b11, op1 = 0b101, CRn = 0b0001, CRm = 0b0000, op2 = 0b011)

if !(IsFeatureImplemented(FEAT_SCTLR2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR_EL3().SCTLR2En == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem(0x278) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && SCR_EL3().SCTLR2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else SCTLR2_EL1() = X{64}(t); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then SCTLR2_EL1() = X{64}(t); else Undefined(); end; end;

When FEAT_SRMASK is implemented:

MRS <Xt>, SCTLR2ALIAS_EL1

(op0 = 0b11, op1 = 0b000, CRn = 0b0001, CRm = 0b0100, op2 = 0b111)

if !(IsFeatureImplemented(FEAT_SCTLR2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && SCR_EL3().SCTLR2En == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().TRVM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGRTR2_EL2().nSCTLR2ALIAS_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().SCTLR2En == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().SCTLR2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x278); else X{64}(t) = SCTLR2_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().SCTLR2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = SCTLR2_EL2(); else X{64}(t) = SCTLR2_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = SCTLR2_EL1(); end;

When FEAT_SRMASK is implemented:

MSR SCTLR2ALIAS_EL1, <Xt>

(op0 = 0b11, op1 = 0b000, CRn = 0b0001, CRm = 0b0100, op2 = 0b111)

if !(IsFeatureImplemented(FEAT_SCTLR2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && SCR_EL3().SCTLR2En == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().TVM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGWTR2_EL2().nSCTLR2ALIAS_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().SCTLR2En == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().SCTLR2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x278) = X{64}(t); else SCTLR2_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().SCTLR2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then SCTLR2_EL2() = X{64}(t); else SCTLR2_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then SCTLR2_EL1() = X{64}(t); end;

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