MPAM ID Register (EL1)
Indicates the presence and maximum PARTID and PMG values supported in the implementation. It also indicates whether the implementation supports MPAM virtualization.
This register is present only when FEAT_MPAM is implemented. Otherwise, direct accesses to MPAMIDR_EL1 are UNDEFINED.
MPAMIDR_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | HAS_SDEFLT | HAS_FORCE_NS | SP4 | HAS_TIDR | HAS_ALTSP | HAS_BW_CTRL | RES0 | PMG_MAX | |||||||||||||||||||||||
| RES0 | VPMR_MAX | HAS_HCR | RES0 | PARTID_MAX | |||||||||||||||||||||||||||
MPAMIDR_EL1 indicates the MPAM implementation parameters of the PE.
Reserved, RES0.
HAS_SDEFLT indicates support for MPAM3_EL3.SDEFLT bit.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| HAS_SDEFLT | Meaning |
|---|---|
| 0b0 |
The SDEFLT bit is not implemented in MPAM3_EL3. |
| 0b1 |
The SDEFLT bit is implemented in MPAM3_EL3. |
When MPAM3_EL3.SDEFLT == 1, accesses from the Secure Execution state use the default PARTID, PARTID == 0.
Access to this field is RO.
HAS_FORCE_NS indicates support for MPAM3_EL3.FORCE_NS bit.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| HAS_FORCE_NS | Meaning |
|---|---|
| 0b0 |
The FORCE_NS bit is not implemented in MPAM3_EL3. |
| 0b1 |
The FORCE_NS bit is implemented in MPAM3_EL3. |
When MPAM3_EL3.FORCE_NS == 1, accesses from the Secure Execution state have MPAM_NS == 1.
Access to this field is RO.
Supports 4 MPAM PARTID spaces.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| SP4 | Meaning |
|---|---|
| 0b0 |
MPAM supports 2 PARTID spaces. |
| 0b1 |
MPAM supports 4 PARTID spaces. |
Access to this field is RO.
HAS_TIDR indicates support for MPAM2_EL2.TIDR bit.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| HAS_TIDR | Meaning |
|---|---|
| 0b0 |
The TIDR bit is not implemented in MPAM2_EL2. |
| 0b1 |
The TIDR bit is implemented in MPAM2_EL2. |
Arm recommends that when the MPAM version is MPAM v0.1 or MPAM v1.1, MPAMIDR_EL1.HAS_TIDR is 1 and that the MPAM2_EL2.TIDR field is implemented.
Access to this field is RO.
HAS_ALTSP indicates support for alternative PARTID spaces.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| HAS_ALTSP | Meaning |
|---|---|
| 0b0 |
Alternative PARTID spaces are not implemented. |
| 0b1 |
Alternative PARTID spaces are implemented with control bits in MPAM3_EL3 and MPAM2_EL2. |
Access to this field is RO.
HAS_BW_CTRL indicates support for PE-side bandwidth controls.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| HAS_BW_CTRL | Meaning |
|---|---|
| 0b0 |
PE-side bandwidth controls are not implemented. |
| 0b1 |
PE-side bandwidth controls are implemented. |
FEAT_MPAM_PE_BW_CTRL implements the functionality identified by the value 0b1.
Access to this field is RO.
Reserved, RES0.
The largest value of PMG that the implementation can generate. The PMG_I and PMG_D fields of every MPAMn_ELx must implement at least enough bits to represent PMG_MAX.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Reserved, RES0.
Indicates the maximum register index n for the MPAMVPM<n>_EL2 registers.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Reserved, RAZ.
HAS_HCR indicates that the PE implementation supports MPAM virtualization, including MPAMHCR_EL2, MPAMVPMV_EL2, and MPAMVPM<n>_EL2 with n in the range 0 to VPMR_MAX. Must be 0 if EL2 is not implemented in either Security state.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| HAS_HCR | Meaning |
|---|---|
| 0b0 |
MPAM virtualization is not supported. |
| 0b1 |
MPAM virtualization is supported. |
Access to this field is RO.
Reserved, RES0.
The largest value of PARTID that the implementation can generate. The PARTID_I and PARTID_D fields of every MPAMn_ELx must implement at least enough bits to represent PARTID_MAX.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, MPAMIDR_EL1
(op0 = 0b11, op1 = 0b000, CRn = 0b1010, CRm = 0b0100, op2 = 0b100)
if !IsFeatureImplemented(FEAT_MPAM) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MPAM3_EL3.TRAPLOWER == '1' then UNDEFINED; elsif HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && MPAMIDR_EL1.HAS_HCR == '1' && MPAMHCR_EL2.TRAP_MPAMIDR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MPAMIDR_EL1.HAS_TIDR == '1' && MPAM2_EL2.TIDR == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = MPAMIDR_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MPAM3_EL3.TRAPLOWER == '1' then UNDEFINED; elsif HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = MPAMIDR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = MPAMIDR_EL1;
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