MPAM PE-side Maximum Bandwidth Limit Virtualization Register
Allows software executing at EL2 to provide MPAMBWCAP_EL2.CAP as an upper bound to MPAMBW1_EL1.MAX.
If FEAT_SME is implemented, the upper bound also applies to MPAMBWSM_EL1.MAX when executing at EL1: the maximum bandwidth allowed for the PE is MIN(MPAMBWSM_EL1.MAX, MPAMBWCAP_EL2.CAP).
If the Effective value of HCR_EL2.{E2H,TGE} is not {1,1}:
If MPAMBWCAP_EL2.ENABLED is 1, a PARTID that has used more than min(CAP,MAX) is given no access to additional bandwidth.
This register is present only when FEAT_MPAM_PE_BW_CTRL is implemented, MPAMIDR_EL1.HAS_HCR == '1', and FEAT_AA64EL2 is implemented. Otherwise, direct accesses to MPAMBWCAP_EL2 are UNDEFINED.
This register has no effect if EL2 is not enabled in the current Security state.
MPAMBWCAP_EL2 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HW_SCALE_ENABLE | ENABLED | RES0 | |||||||||||||||||||||||||||||
| CAP | |||||||||||||||||||||||||||||||
Enables hardware bandwidth scaling of the MPAMBWCAP_EL2.CAP value.
| HW_SCALE_ENABLE | Meaning |
|---|---|
| 0b0 |
PE-side memory bandwidth control hardware scaling for EL2 capping is disabled. |
| 0b1 |
PE-side memory bandwidth control hardware scaling for EL2 capping is enabled. |
The reset behavior of this field is:
Reserved, RES0.
Enables the PE-side memory bandwidth control capping by EL2.
| ENABLED | Meaning |
|---|---|
| 0b0 |
The PE-side memory bandwidth control capping by EL2 is disabled. |
| 0b1 |
The PE-side memory bandwidth control capping by EL2 is enabled. |
The reset behavior of this field is:
Reserved, RES0.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CAP | |||||||||||||||||||||||||||||||
Upper bound to the maximum memory bandwidth allocated to the current PARTID in MPAMBW1_EL1.MAX, MPAMBW0_EL1.MAX and MPAMBWSM_EL1.MAX.
The value is represented as a multiplier of the available bandwidth for the PE. The value is represented in base-2 fixed-point format.
Bits [31:16] represent the integer part of the value.
Bits [15:(16 - MPAMBWIDR_EL1.BWA_WD)] represent the fractional part of the value. When MPAMBWIDR_EL1.BWA_WD indicates a width less than 16 bits, bits [(15 - MPAMBWIDR_EL1.BWA_WD):0] are RES0.
The value set in the MAX field must be less than or equal to this upper bound.
The reset behavior of this field is:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | CAP | ||||||||||||||||||||||||||||||
Reserved, RES0.
Upper bound to the maximum memory bandwidth allocated to the current PARTID in MPAMBW1_EL1.MAX, MPAMBW0_EL1.MAX and MPAMBWSM_EL1.MAX.
The value is represented as a fraction of the available bandwidth for the PE. The value is represented in base-2 fixed-point format.
Bits [15:(16 - MPAMBWIDR_EL1.BWA_WD)] represent the fractional part of the value. When MPAMBWIDR_EL1.BWA_WD indicates a width less than 16 bits, bits [(15 - MPAMBWIDR_EL1.BWA_WD):0] are RES0.
The value set in the MAX field must be less than or equal to this upper bound.
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, MPAMBWCAP_EL2
(op0 = 0b11, op1 = 0b100, CRn = 0b1010, CRm = 0b0101, op2 = 0b110)
if !(IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL) && MPAMIDR_EL1().HAS_HCR == '1' && IsFeatureImplemented(FEAT_AA64EL2)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && MPAMBW3_EL3().nTRAPLOWER == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = NVMem(0x910); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MPAMBW3_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else AArch64_SystemAccessTrap(EL2, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MPAMBW3_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = MPAMBWCAP_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = MPAMBWCAP_EL2(); end;
MSR MPAMBWCAP_EL2, <Xt>
(op0 = 0b11, op1 = 0b100, CRn = 0b1010, CRm = 0b0101, op2 = 0b110)
if !(IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL) && MPAMIDR_EL1().HAS_HCR == '1' && IsFeatureImplemented(FEAT_AA64EL2)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && MPAMBW3_EL3().nTRAPLOWER == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem(0x910) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MPAMBW3_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else AArch64_SystemAccessTrap(EL2, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MPAMBW3_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else MPAMBWCAP_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then MPAMBWCAP_EL2() = X{64}(t); end;
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