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MPAMBW2_EL2

MPAM PE-side Maximum Bandwidth Control Register (EL2)

Enables software to configure a maximum fraction of memory bandwidth that the PE is permitted to use when executing at EL2 with its current PARTID.

Configuration

This register is present only when FEAT_MPAM_PE_BW_CTRL is implemented and FEAT_AA64EL2 is implemented. Otherwise, direct accesses to MPAMBW2_EL2 are UNDEFINED.

This register has no effect if EL2 is not enabled in the current Security state.

Attributes

MPAMBW2_EL2 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
HW_SCALE_ENABLEENABLEDHARDLIMRES0nTRAP_MPAMBWIDR_EL1nTRAP_MPAMBW0_EL1nTRAP_MPAMBW1_EL1nTRAP_MPAMBWSM_EL1RES0
MAX

HW_SCALE_ENABLE, bit [63] when MPAMBWIDR_EL1.HAS_HW_SCALE == '1':

Enables hardware bandwidth scaling of the MPAMBW2_EL2.MAX value.

HW_SCALE_ENABLEMeaning
0b0

PE-side memory bandwidth control hardware scaling at EL2 is disabled.

0b1

PE-side memory bandwidth control hardware scaling at EL2 is enabled.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

ENABLED, bit [62]:

Enables the PE-side memory bandwidth control when at EL2.

ENABLEDMeaning
0b0

The PE-side memory bandwidth control at EL2 is disabled.

0b1

The PE-side memory bandwidth control at EL2 is enabled.

The reset behavior of this field is:

HARDLIM, bit [61]:

PE-side Maximum Bandwidth Limit Behavior Selection.

HARDLIMMeaning
0b0

Soft limit: when MPAMBW2_EL2.MAX bandwidth is exceeded, the PE is unregulated unless the downstream memory path is saturated. It is IMPLEMENTATION DEFINED how hardware determines when the downstream memory path is saturated.

0b1

Hard limit: when MPAMBW2_EL2.MAX bandwidth is exceeded, the PE does not use any more bandwidth until the memory bandwidth for the PE falls below MPAMBW2_EL2.MAX.

The reset behavior of this field is:

Accessing this field has the following behavior:

Bits [60:53]:

Reserved, RES0.

nTRAP_MPAMBWIDR_EL1, bit [52]:

Traps accesses to MPAMBWIDR_EL1 from EL1 to EL2.

nTRAP_MPAMBWIDR_EL1Meaning
0b0

Accesses to MPAMBWIDR_EL1 from EL1 are trapped to EL2 with EC syndrome value 0x18.

0b1

Accesses to MPAMBWIDR_EL1 from EL1 are not trapped by this mechanism.

The reset behavior of this field is:

nTRAP_MPAMBW0_EL1, bit [51]:

Traps accesses to MPAMBW0_EL1 from EL1 to EL2.

nTRAP_MPAMBW0_EL1Meaning
0b0

Accesses to MPAMBW0_EL1 from EL1 are trapped to EL2 with EC syndrome value 0x18.

0b1

Accesses to MPAMBW0_EL1 from EL1 are not trapped by this mechanism.

The reset behavior of this field is:

nTRAP_MPAMBW1_EL1, bit [50]:

Traps accesses to MPAMBW1_EL1 from EL1 to EL2.

nTRAP_MPAMBW1_EL1Meaning
0b0

Accesses to MPAMBW1_EL1 from EL1 are trapped to EL2 with EC syndrome value 0x18.

0b1

Accesses to MPAMBW1_EL1 from EL1 are not trapped by this mechanism.

The reset behavior of this field is:

nTRAP_MPAMBWSM_EL1, bit [49] when FEAT_SME is implemented:

Traps accesses to MPAMBWSM_EL1 from EL1 to EL2.

nTRAP_MPAMBWSM_EL1Meaning
0b0

Accesses to MPAMBWSM_EL1 from EL1 are trapped to EL2 with EC syndrome value 0x18.

0b1

Accesses to MPAMBWSM_EL1 from EL1 are not trapped by this mechanism.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Bits [48:32]:

Reserved, RES0.

MAX, bits [31:0]:

MAX encoding when MPAMBWIDR_EL1.HAS_HW_SCALE == '1' and MPAMBW2_EL2.HW_SCALE_ENABLE == '1'

313029282726252423222120191817161514131211109876543210
MAX

MAX, bits [31:0]:

Maximum memory bandwidth allocated to the PE when executing at EL2 with its current PARTID.

The value is represented as a multiplier of the available bandwidth for the PE. The value is represented in base-2 fixed-point format.

Bits [31:16] represent the integer part of the value.

Bits [15:(16 - MPAMBWIDR_EL1.BWA_WD)] represent the fractional part of the value. When MPAMBWIDR_EL1.BWA_WD indicates a width less than 16 bits, bits [(15 - MPAMBWIDR_EL1.BWA_WD):0] are RES0.

The reset behavior of this field is:

  • On a Warm reset, this field resets to an architecturally UNKNOWN value.

MAX encoding when MPAMBWIDR_EL1.HAS_HW_SCALE == '0' or MPAMBW2_EL2.HW_SCALE_ENABLE == '0'

313029282726252423222120191817161514131211109876543210
RES0MAX

Bits [31:16]:

Reserved, RES0.

MAX, bits [15:0]:

Maximum memory bandwidth allocated to the PE when executing at EL2 with its current PARTID.

The value is represented as a fraction of the available bandwidth for the PE. The value is represented in base-2 fixed-point format.

Bits [15:(16 - MPAMBWIDR_EL1.BWA_WD)] represent the fractional part of the value. When MPAMBWIDR_EL1.BWA_WD indicates a width less than 16 bits, bits [(15 - MPAMBWIDR_EL1.BWA_WD):0] are RES0.

The reset behavior of this field is:

  • On a Warm reset, this field resets to an architecturally UNKNOWN value.

Access Instructions

When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL2 using the accessor name MPAMBW2_EL2 or MPAMBW1_EL1 are not guaranteed to be ordered with respect to accesses using the other accessor name.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, MPAMBW2_EL2

(op0 = 0b11, op1 = 0b100, CRn = 0b1010, CRm = 0b0101, op2 = 0b100)

if !(IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL) && IsFeatureImplemented(FEAT_AA64EL2)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && MPAMBW3_EL3().nTRAPLOWER == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MPAMBW3_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else AArch64_SystemAccessTrap(EL2, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MPAMBW3_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = MPAMBW2_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = MPAMBW2_EL2(); end;

MSR MPAMBW2_EL2, <Xt>

(op0 = 0b11, op1 = 0b100, CRn = 0b1010, CRm = 0b0101, op2 = 0b100)

if !(IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL) && IsFeatureImplemented(FEAT_AA64EL2)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && MPAMBW3_EL3().nTRAPLOWER == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MPAMBW3_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else AArch64_SystemAccessTrap(EL2, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MPAMBW3_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else MPAMBW2_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then MPAMBW2_EL2() = X{64}(t); end;

When FEAT_VHE is implemented:

MRS <Xt>, MPAMBW1_EL1

(op0 = 0b11, op1 = 0b000, CRn = 0b1010, CRm = 0b0101, op2 = 0b100)

if !IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && MPAMBW3_EL3().nTRAPLOWER == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MPAMBW3_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EL2Enabled() && MPAMBW2_EL2().nTRAP_MPAMBW1_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x908); else X{64}(t) = MPAMBW1_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MPAMBW3_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = MPAMBW2_EL2(); else X{64}(t) = MPAMBW1_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = MPAMBW1_EL1(); end;

When FEAT_VHE is implemented:

MSR MPAMBW1_EL1, <Xt>

(op0 = 0b11, op1 = 0b000, CRn = 0b1010, CRm = 0b0101, op2 = 0b100)

if !IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && MPAMBW3_EL3().nTRAPLOWER == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MPAMBW3_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EL2Enabled() && MPAMBW2_EL2().nTRAP_MPAMBW1_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x908) = X{64}(t); else MPAMBW1_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAMv2) && MPAMCTL_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MPAMBW3_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then MPAMBW2_EL2() = X{64}(t); else MPAMBW1_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then MPAMBW1_EL1() = X{64}(t); end;

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