MECID_RL_A_EL3

Realm PA space Alternate MECID for EL3 stage 1 translation regime

Alternate MECID for EL3 accesses to the Realm physical address space, translated by TTBR0_EL3.

Configuration

This register is present only when FEAT_MEC is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to MECID_RL_A_EL3 are UNDEFINED.

Attributes

MECID_RL_A_EL3 is a 64-bit register.

Field descriptions

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0																MECID

Bits [63:16]:

Reserved, RES0.

MECID, bits [15:0]:

If MECIDWidth is less than 16 bits, bits[15:MECIDWidth] are RES0.

MECIDWidth is defined in MECIDR_EL2.MECIDWidthm1.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, MECID_RL_A_EL3

(op0 = 0b11, op1 = 0b110, CRn = 0b1010, CRm = 0b1010, op2 = 0b001)

if !(IsFeatureImplemented(FEAT_MEC) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then X{64}(t) = MECID_RL_A_EL3(); end;

MSR MECID_RL_A_EL3, <Xt>

(op0 = 0b11, op1 = 0b110, CRn = 0b1010, CRm = 0b1010, op2 = 0b001)

if !(IsFeatureImplemented(FEAT_MEC) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_FGWTE3) && FGWTE3_EL3().MECID_RL_A_EL3 == '1' then AArch64_SystemAccessTrap(EL3, 0x18); else MECID_RL_A_EL3() = X{64}(t); end; end;

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