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MECIDR_EL2: MEC Identification Register

Purpose

MEC identification register.

Configuration

This register is present only when FEAT_MEC is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to MECIDR_EL2 are UNDEFINED.

If EL2 is not implemented, this register is RES0 from EL3.

Attributes

MECIDR_EL2 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0MECIDWidthm1

Bits [63:4]

Reserved, RES0.

MECIDWidthm1, bits [3:0]

MECID width minus 1.

The value of this field plus 1 is the MECID width in bits, that this PE supports.

For example, the value 0b1111 indicates that this PE supports a MECID width of 16 bits, and provides 216 possible MECID values.

MECIDWidth is defined as MECIDR_EL2.MECIDWidthm1 + 1.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Accessing MECIDR_EL2

For accesses from EL2 and EL3, this register is RO.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, MECIDR_EL2

op0op1CRnCRmop2
0b110b1000b10100b10000b111

if !(IsFeatureImplemented(FEAT_MEC) && IsFeatureImplemented(FEAT_AA64)) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then X[t, 64] = MECIDR_EL2; elsif PSTATE.EL == EL3 then X[t, 64] = MECIDR_EL2;