AArch64 Processor Feature Register 2
Provides additional information about implemented PE features in AArch64 state.
For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'.
This register is present only when FEAT_AA64 is implemented. Otherwise, direct accesses to ID_AA64PFR2_EL1 are UNDEFINED.
Prior to the introduction of the features described by this register, this register was unnamed and reserved, RES0 from EL1, EL2, and EL3.
ID_AA64PFR2_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | FPMR | ||||||||||||||||||||||||||||||
| MPAM2 | RES0 | MTEEIRG | UINJ | GCIE | MTEFAR | MTESTOREONLY | MTEPERM | ||||||||||||||||||||||||
Reserved, RES0.
Indicates support for FPMR.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| FPMR | Meaning |
|---|---|
| 0b0000 |
FPMR is not implemented. |
| 0b0001 |
FPMR is implemented. |
All other values are reserved.
FEAT_FPMR implements the functionality identified by the value 0b0001.
Access to this field is RO.
Support for MPAM 2 Extension.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| MPAM2 | Meaning |
|---|---|
| 0b0000 |
MPAM 2 extension is not implemented. |
| 0b0001 |
MPAM 2 extension is implemented. |
All other values are reserved.
FEAT_MPAMv2 implements the functionality identified by the value 0b0001.
If this field is not 0b0000, then ID_AA64PFR0_EL1.MPAM and ID_AA64PFR1_EL1.MPAM_frac must both be 0b0000.
For more information, see 'The Memory Partitioning and Monitoring (MPAM) Extension'.
Access to this field is RO.
Reserved, RES0.
Support for the Enhanced Insert Random taG algorithm.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| MTEEIRG | Meaning |
|---|---|
| 0b0000 |
The Enhanced Insert Random taG algorithm is not implemented. |
| 0b0001 |
The Enhanced Insert Random taG algorithm is implemented. |
FEAT_MTE_EIRG implements the functionality identified by the value 0b0001.
From Armv9.7, if FEAT_MTE2 is implemented, the value 0b0000 is not permitted.
Access to this field is RO.
Support for software injection of Undefined Instruction exceptions.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| UINJ | Meaning |
|---|---|
| 0b0000 |
Software injection of Undefined Instruction exceptions is not implemented. |
| 0b0001 |
Software injection of Undefined Instruction exceptions is implemented. |
FEAT_UINJ implements the functionality identified by the value 0b0001.
From Armv9.6, the value 0b0000 is not permitted.
Access to this field is RO.
Support for the GICv5 CPU interface extension.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| GCIE | Meaning |
|---|---|
| 0b0000 |
FEAT_GCIE is not supported. |
| 0b0001 |
FEAT_GCIE is supported. |
Access to this field is RO.
Indicates whether FAR_ELx[63:60] are UNKNOWN on a synchronous exception due to a Tag Check Fault.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| MTEFAR | Meaning |
|---|---|
| 0b0000 |
On a synchronous exception due to a Tag Check Fault, FAR_ELx[63:60] are UNKNOWN. |
| 0b0001 |
On a synchronous exception due to a Tag Check Fault, FAR_ELx[63:60] are not UNKNOWN. |
All other values are reserved.
FEAT_MTE_TAGGED_FAR implements the functionality identified by the value 0b0001.
If FEAT_MTE2 is not implemented, the value 0b0001 is not permitted.
From Armv8.9, if FEAT_MTE2 is implemented, the value 0b0000 is not permitted.
Access to this field is RO.
Support for Store-only Tag checking.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| MTESTOREONLY | Meaning |
|---|---|
| 0b0000 |
Store-only Tag checking is not supported. |
| 0b0001 |
Store-only Tag checking is supported. |
All other values are reserved.
FEAT_MTE_STORE_ONLY implements the functionality identified by the value 0b0001.
If FEAT_MTE2 is not implemented, the value 0b0001 is not permitted.
From Armv8.9, if FEAT_MTE2 is implemented, the value 0b0000 is not permitted.
Access to this field is RO.
Support for Allocation tag access permissions.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| MTEPERM | Meaning |
|---|---|
| 0b0000 |
Allocation tag access permissions are not supported. |
| 0b0001 | Allocation tag access permissions are supported. NoTagAccess is supported at stage 2 of translation only. |
All other values are reserved.
FEAT_MTE_PERM implements the functionality identified by the value 0b0001
If FEAT_MTE2 is not implemented, the value 0b0001 is not permitted.
From Armv8.9, if FEAT_MTE2 is implemented, the value 0b0000 is not permitted.
Access to this field is RO.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, ID_AA64PFR2_EL1
(op0 = 0b11, op1 = 0b000, CRn = 0b0000, CRm = 0b0100, op2 = 0b010)
if !IsFeatureImplemented(FEAT_AA64) then UnimplementedIDRegister(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then AArch64_SystemAccessTraptoEL1orEL2(0x18); else Undefined(); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && (IsFeatureImplemented(FEAT_FGT) || !IsZero(ID_AA64PFR2_EL1()) || ImpDefBool("ID_AA64PFR2_EL1 trapped by HCR_EL2.TID3")) && HCR_EL2().TID3 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_AA64PFR2_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_AA64PFR2_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = ID_AA64PFR2_EL1(); end;
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