ICV_PPI_CPENDR<n>_EL1 | Jon's Arm Reference

AArch64 System register ICV_PPI_CPENDR<n>_EL1 bits [63:0] are architecturally mapped to AArch64 System register ICH_PPI_PENDR<n>_EL2[63:0].

AArch64 System register ICV_PPI_CPENDR<n>_EL1 bits [63:0] are architecturally mapped to AArch64 System register ICV_PPI_SPENDR<n>_EL1[63:0].

This register is present only when FEAT_GCIE is implemented, EL2 is implemented, and FEAT_AA64 is implemented. Otherwise, direct accesses to ICV_PPI_CPENDR<n>_EL1 are UNDEFINED.

Attributes

Field descriptions

PEND<x>, bit [x], for x = 63 to 0:

PPI <(n * 64) + x> Pending state.

Reads return the current state of the PPI.

Writing 1 to a field clears the Pending state of the PPI. Writing 0 has no effect.

PEND<x>	Meaning
0b0	Not pending
0b1	Pending

When the Pending state of a physical PPI is directly injected to the Pending state of virtual PPI <x>, all of the following are true:

Reads of Pend<x> return the value of the field corresponding to the physical PPI in ICC_PPI_CPENDR<n>_EL1.
Writes to Pend<x> have the same effect as writes to the field corresponding to the physical PPI in ICC_PPI_CPENDR<n>_EL1.

Otherwise, all of the following are true:

Reads of Pend<x> return the value of ICH_PPI_PENDR<n>_EL2.Pend<x>.
Writes to Pend<x> update the value of ICH_PPI_PENDR<n>_EL2.Pend<x>.

The reset behavior of this field is:

On a Warm reset, this field resets to an UNKNOWN value.

Accessing this field has the following behavior:

When !IsPPIImplemented((n * 64) + x), access to this field is RAZ/WI.
When ICV_PPI_HMR_EL1[n].HM<x> == '1', access to this field is RO.
Otherwise, access to this field is W1C.

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, ICC_PPI_CPENDR<n>_EL1 ; Where n = 0-1

(op0 = 0b11, op1 = 0b000, CRn = 0b1100, CRm = 0b1101, op2 = 0b10:n[0])

let n:integer = UInt(op2[0]); if !(IsFeatureImplemented(FEAT_GCIE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().IMO == '1' && IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '1' then Undefined(); elsif EL2Enabled() && ICH_HFGRTR_EL2().ICC_PPI_PENDRn_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().IMO == '1' then X{64}(t) = ICV_PPI_CPENDR_EL1(n); else X{64}(t) = ICC_PPI_CPENDR_EL1(n); end; elsif PSTATE.EL == EL2 then X{64}(t) = ICC_PPI_CPENDR_EL1(n); elsif PSTATE.EL == EL3 then X{64}(t) = ICC_PPI_CPENDR_EL1(n); end;

MSR ICC_PPI_CPENDR<n>_EL1, <Xt> ; Where n = 0-1

(op0 = 0b11, op1 = 0b000, CRn = 0b1100, CRm = 0b1101, op2 = 0b10:n[0])

let n:integer = UInt(op2[0]); if !(IsFeatureImplemented(FEAT_GCIE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().IMO == '1' && IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '1' then Undefined(); elsif EL2Enabled() && ICH_HFGWTR_EL2().ICC_PPI_PENDRn_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().IMO == '1' then ICV_PPI_CPENDR_EL1(n) = X{64}(t); else ICC_PPI_CPENDR_EL1(n) = X{64}(t); end; elsif PSTATE.EL == EL2 then ICC_PPI_CPENDR_EL1(n) = X{64}(t); elsif PSTATE.EL == EL3 then ICC_PPI_CPENDR_EL1(n) = X{64}(t); end;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PEND63	PEND62	PEND61	PEND60	PEND59	PEND58	PEND57	PEND56	PEND55	PEND54	PEND53	PEND52	PEND51	PEND50	PEND49	PEND48	PEND47	PEND46	PEND45	PEND44	PEND43	PEND42	PEND41	PEND40	PEND39	PEND38	PEND37	PEND36	PEND35	PEND34	PEND33	PEND32
PEND31	PEND30	PEND29	PEND28	PEND27	PEND26	PEND25	PEND24	PEND23	PEND22	PEND21	PEND20	PEND19	PEND18	PEND17	PEND16	PEND15	PEND14	PEND13	PEND12	PEND11	PEND10	PEND9	PEND8	PEND7	PEND6	PEND5	PEND4	PEND3	PEND2	PEND1	PEND0

ICV_PPI_CPENDR<n>_EL1, n = 0 - 1

Configuration

Attributes

Field descriptions

PEND<x>, bit [x], for x = 63 to 0:

Access Instructions