Interrupt Controller Virtual Interrupt Pending State Registers
Pending state for virtual PPIs.
AArch64 System register ICH_PPI_PENDR<n>_EL2 bits [63:0] are architecturally mapped to AArch64 System register ICV_PPI_CPENDR<n>_EL1[63:0].
AArch64 System register ICH_PPI_PENDR<n>_EL2 bits [63:0] are architecturally mapped to AArch64 System register ICV_PPI_SPENDR<n>_EL1[63:0].
This register is present only when FEAT_GCIE is implemented, (EL2 is implemented or EL3 is implemented), and FEAT_AA64 is implemented. Otherwise, direct accesses to ICH_PPI_PENDR<n>_EL2 are UNDEFINED.
If EL2 is not implemented, this register is RES0 from EL3.
ICH_PPI_PENDR<n>_EL2 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PEND63 | PEND62 | PEND61 | PEND60 | PEND59 | PEND58 | PEND57 | PEND56 | PEND55 | PEND54 | PEND53 | PEND52 | PEND51 | PEND50 | PEND49 | PEND48 | PEND47 | PEND46 | PEND45 | PEND44 | PEND43 | PEND42 | PEND41 | PEND40 | PEND39 | PEND38 | PEND37 | PEND36 | PEND35 | PEND34 | PEND33 | PEND32 |
| PEND31 | PEND30 | PEND29 | PEND28 | PEND27 | PEND26 | PEND25 | PEND24 | PEND23 | PEND22 | PEND21 | PEND20 | PEND19 | PEND18 | PEND17 | PEND16 | PEND15 | PEND14 | PEND13 | PEND12 | PEND11 | PEND10 | PEND9 | PEND8 | PEND7 | PEND6 | PEND5 | PEND4 | PEND3 | PEND2 | PEND1 | PEND0 |
Virtual PPI <(n * 64) + x> Pending state.
| PEND<x> | Meaning |
|---|---|
| 0b0 |
Not pending |
| 0b1 |
Pending |
Accessing this field has the following behavior:
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, ICH_PPI_PENDR<n>_EL2 ; Where n = 0-1
(op0 = 0b11, op1 = 0b100, CRn = 0b1100, CRm = 0b1010, op2 = 0b10:n[0])
let n:integer = UInt(op2[0]); if !(IsFeatureImplemented(FEAT_GCIE) && (HaveEL(EL2) || HaveEL(EL3)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then X{64}(t) = ICH_PPI_PENDR_EL2(n); elsif PSTATE.EL == EL3 then X{64}(t) = ICH_PPI_PENDR_EL2(n); end;
MSR ICH_PPI_PENDR<n>_EL2, <Xt> ; Where n = 0-1
(op0 = 0b11, op1 = 0b100, CRn = 0b1100, CRm = 0b1010, op2 = 0b10:n[0])
let n:integer = UInt(op2[0]); if !(IsFeatureImplemented(FEAT_GCIE) && (HaveEL(EL2) || HaveEL(EL3)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then ICH_PPI_PENDR_EL2(n) = X{64}(t); elsif PSTATE.EL == EL3 then ICH_PPI_PENDR_EL2(n) = X{64}(t); end;
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