Interrupt Controller System Register Enable Register (EL1)
Controls whether the System register interface or the memory-mapped interface to the GIC CPU interface is used for EL1.
This register is banked between ICC_SRE_EL1 and ICC_SRE_EL1_S and ICC_SRE_EL1_NS.
AArch64 System register ICC_SRE_EL1 bits [31:0] (ICC_SRE_EL1_S) are architecturally mapped to AArch32 System register ICC_SRE[31:0] (ICC_SRE_S).
AArch64 System register ICC_SRE_EL1 bits [31:0] (ICC_SRE_EL1_NS) are architecturally mapped to AArch32 System register ICC_SRE[31:0] (ICC_SRE_NS).
AArch64 System register ICC_SRE_EL1 bits [31:0] are architecturally mapped to AArch32 System register ICC_SRE.
This register is present only when (GICv3 is implemented or (FEAT_GCIE is implemented and EL2 is implemented)) and FEAT_AA64 is implemented. Otherwise, direct accesses to ICC_SRE_EL1 are UNDEFINED.
ICC_SRE_EL1 is a 64-bit register.
This register has the following instances:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | DIB | DFB | SRE | ||||||||||||||||||||||||||||
Reserved, RES0.
Disable IRQ bypass.
| DIB | Meaning |
|---|---|
| 0b0 |
IRQ bypass enabled. |
| 0b1 |
IRQ bypass disabled. |
If EL3 is implemented and GICD_CTLR.DS == 0, this field is a read-only alias of ICC_SRE_EL3.DIB.
If EL3 is implemented and GICD_CTLR.DS == 1, and EL2 is not implemented, this field is a read/write alias of ICC_SRE_EL3.DIB.
If EL3 is not implemented and EL2 is implemented, this field is a read-only alias of ICC_SRE_EL2.DIB.
If GICD_CTLR.DS == 1 and EL2 is implemented, this field is a read-only alias of ICC_SRE_EL2.DIB.
In systems that do not support IRQ bypass, this field is RAO/WI.
The reset behavior of this field is:
When FEAT_GCIE is implemented, access to this field is RAO/WI.
Disable FIQ bypass.
| DFB | Meaning |
|---|---|
| 0b0 |
FIQ bypass enabled. |
| 0b1 |
FIQ bypass disabled. |
If EL3 is implemented and GICD_CTLR.DS == 0, this field is a read-only alias of ICC_SRE_EL3.DFB.
If EL3 is implemented and GICD_CTLR.DS == 1, and EL2 is not implemented, this field is a read/write alias of ICC_SRE_EL3.DFB.
If EL3 is not implemented and EL2 is implemented, this field is a read-only alias of ICC_SRE_EL2.DFB.
If GICD_CTLR.DS == 1 and EL2 is implemented, this field is a read-only alias of ICC_SRE_EL2.DFB.
In systems that do not support FIQ bypass, this field is RAO/WI.
The reset behavior of this field is:
When FEAT_GCIE is implemented, access to this field is RAO/WI.
System Register Enable.
| SRE | Meaning |
|---|---|
| 0b0 |
The memory-mapped interface must be used. Access at EL1 to any ICC_* System register other than ICC_SRE_EL1 is trapped to EL1. |
| 0b1 |
The System register interface for the current Security state is enabled. |
If software changes this bit from 1 to 0 in the Secure instance of this register, the results are UNPREDICTABLE.
If an implementation supports only a System register interface to the GIC CPU interface, this bit is RAO/WI.
If EL3 is implemented and ICC_SRE_EL3.SRE==0 the Secure copy of this bit is RAZ/WI. If ICC_SRE_EL3.SRE is changed from zero to one, the Secure copy of this bit becomes UNKNOWN.
If EL2 is implemented and ICC_SRE_EL2.SRE==0 the Non-secure copy of this bit is RAZ/WI. If ICC_SRE_EL2.SRE is changed from zero to one, the Non-secure copy of this bit becomes UNKNOWN.
If EL3 is implemented and ICC_SRE_EL3.SRE==0 the Non-secure copy of this bit is RAZ/WI. If ICC_SRE_EL3.SRE is changed from zero to one, the Non-secure copy of this bit becomes UNKNOWN.
If Realm Management Extension is implemented, this field is RAO/WI.
GICv3 implementations that do not require GICv2 compatibility might choose to make this bit RAO/WI. The following options are supported:
A VM using only virtual interrupts might still use memory-mapped access if the Non-secure copy of ICC_SRE_EL1.SRE is not RAO/WI.
The reset behavior of this field is:
When FEAT_GCIE is implemented, access to this field is RAO/WI.
Execution with ICC_SRE_EL1.SRE set to 0 might make some System registers UNKNOWN.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, ICC_SRE_EL1
(op0 = 0b11, op1 = 0b000, CRn = 0b1100, CRm = 0b1100, op2 = 0b101)
if !((IsFeatureImplemented(FEAT_GICv3) || (IsFeatureImplemented(FEAT_GCIE) && HaveEL(EL2))) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && EffectiveICC_SRE_EL3_Enable() == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && EffectiveICC_SRE_EL2_Enable() == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && EffectiveICC_SRE_EL3_Enable() == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then X{64}(t) = ICC_SRE_EL1_S(); else X{64}(t) = ICC_SRE_EL1_NS(); end; else X{64}(t) = ICC_SRE_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EffectiveICC_SRE_EL3_Enable() == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then X{64}(t) = ICC_SRE_EL1_S(); else X{64}(t) = ICC_SRE_EL1_NS(); end; else X{64}(t) = ICC_SRE_EL1(); end; elsif PSTATE.EL == EL3 then if EffectiveSCR_EL3_NS() == '0' then X{64}(t) = ICC_SRE_EL1_S(); else X{64}(t) = ICC_SRE_EL1_NS(); end; end;
MSR ICC_SRE_EL1, <Xt>
(op0 = 0b11, op1 = 0b000, CRn = 0b1100, CRm = 0b1100, op2 = 0b101)
if !((IsFeatureImplemented(FEAT_GICv3) || (IsFeatureImplemented(FEAT_GCIE) && HaveEL(EL2))) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && EffectiveICC_SRE_EL3_Enable() == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && EffectiveICC_SRE_EL2_Enable() == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && EffectiveICC_SRE_EL3_Enable() == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then ICC_SRE_EL1_S() = X{64}(t); else ICC_SRE_EL1_NS() = X{64}(t); end; else ICC_SRE_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EffectiveICC_SRE_EL3_Enable() == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then ICC_SRE_EL1_S() = X{64}(t); else ICC_SRE_EL1_NS() = X{64}(t); end; else ICC_SRE_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then if EffectiveSCR_EL3_NS() == '0' then ICC_SRE_EL1_S() = X{64}(t); else ICC_SRE_EL1_NS() = X{64}(t); end; end;
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