Interrupt Controller System Register Enable Register (EL3)
Controls whether the System register interface or the memory-mapped interface to the GIC CPU interface is used for EL3.
This register is present only when GICv3 is implemented, EL3 is implemented, and FEAT_AA64 is implemented. Otherwise, direct accesses to ICC_SRE_EL3 are UNDEFINED.
ICC_SRE_EL3 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | Enable | DIB | DFB | SRE | |||||||||||||||||||||||||||
Reserved, RES0.
Enable. Enables lower Exception level access to ICC_SRE_EL1 and ICC_SRE_EL2.
| Enable | Meaning |
|---|---|
| 0b0 | EL1 accesses to ICC_SRE_EL1 trap to EL3, unless these accesses are trapped to EL2 as a result of ICC_SRE_EL2.Enable == 0. EL2 accesses to ICC_SRE_EL1 and ICC_SRE_EL2 trap to EL3. |
| 0b1 | EL1 accesses to ICC_SRE_EL1 do not trap to EL3. EL2 accesses to ICC_SRE_EL1 and ICC_SRE_EL2 do not trap to EL3. |
If ICC_SRE_EL3.SRE is RAO/WI, an implementation is permitted to make the Enable bit RAO/WI.
If ICC_SRE_EL3.SRE is 0, the Enable bit behaves as 1 for all purposes other than reading the value of the bit.
The reset behavior of this field is:
Disable IRQ bypass.
| DIB | Meaning |
|---|---|
| 0b0 |
IRQ bypass enabled. |
| 0b1 |
IRQ bypass disabled. |
In systems that do not support IRQ bypass, this bit is RAO/WI.
The reset behavior of this field is:
Disable FIQ bypass.
| DFB | Meaning |
|---|---|
| 0b0 |
FIQ bypass enabled. |
| 0b1 |
FIQ bypass disabled. |
In systems that do not support FIQ bypass, this bit is RAO/WI.
The reset behavior of this field is:
System Register Enable.
| SRE | Meaning |
|---|---|
| 0b0 |
The memory-mapped interface must be used. Access at EL3 to any ICH_* or ICC_* register other than ICC_SRE_EL1, ICC_SRE_EL2, or ICC_SRE_EL3 is trapped to EL3 |
| 0b1 |
The System register interface to the ICH_* registers and the EL1, EL2, and EL3 ICC_* registers is enabled for EL3. |
If software changes this bit from 1 to 0, the results are UNPREDICTABLE.
If Realm Management Extension is implemented, this field is RAO/WI.
FEAT_GICv3 implementations that do not require GICv2 compatibility might choose to make this bit RAO/WI.
The reset behavior of this field is:
This register is always System register accessible.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, ICC_SRE_EL3
(op0 = 0b11, op1 = 0b110, CRn = 0b1100, CRm = 0b1100, op2 = 0b101)
if !(IsFeatureImplemented(FEAT_GICv3) && HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64)) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then X[t, 64] = ICC_SRE_EL3;
MSR ICC_SRE_EL3, <Xt>
(op0 = 0b11, op1 = 0b110, CRn = 0b1100, CRm = 0b1100, op2 = 0b101)
if !(IsFeatureImplemented(FEAT_GICv3) && HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64)) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then ICC_SRE_EL3 = X[t, 64];
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