Debug Link Register
In Debug state, holds the address to restart from.
AArch64 System register DLR_EL0 bits [31:0] are architecturally mapped to AArch32 System register DLR[31:0].
This register is present only when FEAT_AA64 is implemented. Otherwise, direct accesses to DLR_EL0 are UNDEFINED.
DLR_EL0 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADDR | |||||||||||||||||||||||||||||||
| ADDR | |||||||||||||||||||||||||||||||
Restart address.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, DLR_EL0
(op0 = 0b11, op1 = 0b011, CRn = 0b0100, CRm = 0b0101, op2 = 0b001)
if !IsFeatureImplemented(FEAT_AA64) then UNDEFINED; elsif !Halted() then UNDEFINED; else X[t, 64] = DLR_EL0;
MSR DLR_EL0, <Xt>
(op0 = 0b11, op1 = 0b011, CRn = 0b0100, CRm = 0b0101, op2 = 0b001)
if !IsFeatureImplemented(FEAT_AA64) then UNDEFINED; elsif !Halted() then UNDEFINED; else DLR_EL0 = X[t, 64];
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