DLR

AArch32 System register DLR bits [31:0] are architecturally mapped to AArch64 System register DLR_EL0[31:0].

This register is present only when FEAT_AA32 is implemented. Otherwise, direct accesses to DLR are UNDEFINED.

Attributes

Field descriptions

ADDR, bits [31:0]:

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

(coproc = 0b1111, opc1 = 0b011, CRn = 0b0100, CRm = 0b0101, opc2 = 0b001)

if !IsFeatureImplemented(FEAT_AA32) then UNDEFINED; elsif !Halted() then UNDEFINED; else R[t] = DLR;

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

(coproc = 0b1111, opc1 = 0b011, CRn = 0b0100, CRm = 0b0101, opc2 = 0b001)

if !IsFeatureImplemented(FEAT_AA32) then UNDEFINED; elsif !Halted() then UNDEFINED; else DLR = R[t];

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR